Micron Technology Incorporated

International Business Machines Corporation

Other

Paul A Farrar

Leonard Forbes

Jerome Michael Eldridge

Kie Y Ahn

Arup Bhattacharyya

Joseph E Geusic

Alan R Reinberg

Eugene H Cloud

Hussein Ibrahim Hanafi

John H Givens

Claude Louis Bertin

John Edward Cronin

Luan C Tran

Gordon A Kelley, Jr

Wendell P Noble

Howard L Kalter

Christopher P Miller

Robert Michael Geffken

Harold G Linde

Rosemary A Previti-Kelly

Francis Roger White

David J McElroy

Willem B Van Der Hoeven

Warren M Farnworth

Kevin G Donohoe

William Thomas Motsiff

Wayne John Howell

James Gardner Ryan

Richard Francis Frankeny

Carter W Kaanta

David J Perlman

Jerome A Frankeny

Karl Hermann

Andrew J Watts

Adolf E Wirsing

Javad Haj-ali-Ahmadi

Charles T Kroll

John A Williamson

Herbert Carl Cook

Jacqueline A Shorter-Beauchamp

David J Mcelroy

In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

Semiconductor device with strained channels

Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.

Apparatus and method for high density multi-chip structures

A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.

Apparatus and method for controlling diffusion

The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface 'nanocavities' adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.

Semiconductor device structures including strained transistor channels

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Distributed semiconductor device methods, apparatus, and systems

Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

High density chip packages, methods of forming, and systems including same

Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Structures and methods to enhance copper metallization

Methods for stressing transistor channels of a semiconductor device structure

Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels

Methods of forming strained semiconductor channels

Growing community of inventors

Bluffton, SC, United States of America

Paul A Farrar