Kendall Square Research Corporation

Paul A Binder

Steven J Frank

Henry Burkhardt, Iii

James B Rothnie

David I Epstein

Dana R Kelly

Stephen W Morss

An associative memory having an associativity of 2.sup.q, where (q) is an integer greater than or equal to one, is provided for storing information relating to data. The memory includes (n) tables, each having a plurality of entries for storing signals associated with data descriptors having a common set portion and common other portions. The entries of table (k), where (k) represents successive integers between (1) and (n-1), store pointers to respective entries of table (k+1). The entries of table (1) are arranged for access as a function of the common set portion and the common portion (1) with which they are respectively associated. The entries of the other tables are arranged for access as a function of (i) a value of the common set portion, (ii) a value of a pointer-respresentative signal of the respective table (m-1) entry means, and (iii) the value of the common portion(m) with which such table(m) entry means is respectively associated. The entries of table(n) store information relating to one or more data having a common portion(n).

Dynamic hierarchial associative memory

A digital data communications apparatus includes first and second processing groups, each made up of a plurality of processing cells interconnected by an associated bus. An element (RRC) transfers information packets generated by the processing cells between the first and second processing groups. The RRC includes an input for receiving packets from the bus of the first processing group, as well as first and second outputs for outputting packets to the buses of the first and second groups, respectively. A control element routes packets received at the input to a selected one of the outputs based upon a prior history of routings of the datum referenced in that information packet (or requests for that data) between said first and second processing groups.

Dynamic packet routing network

A switch is provided for selectively routing digital information packets received from at least first and second external sources to at least first and second external destinations. At least one of the first sources generates an information packet including a datum, or a request therefore, and a corresponding descriptor. First and second routing interconnects have inputs for receiving packets from respective sources and outputs for transmitting packets to respective destinations. The interconnects are also coupled for transferring packets between one another. Directories within the interconnects store descriptors corresponding to data associated with the first destination, as well as requests routed from the other interconnect. A controller routes packets based on the correspondence, or lack thereof, between the descriptor in that packet and an entry signal allocated to corresponding directory.

Growing community of inventors

Hollis, NH, United States of America

Paul A Binder