Infineon Technologies Ag

Intel Corporation

Patrizia Greco

Elmar Bach

Martin Clara

Christian Lindholm

Giacomo Cascio

Edwin Thaller

Matteo Camponeschi

Snezana Stojanovic

Michael Fulde

Andreas Steinschaden

Gernot Zessar

Harneet Khurana

Andreas Wiesbauer

Mario Motz

Dietmar Straeussnigg

Daniel Gruber

Lukas Doerrer

Francesco Conzatti

Patrick Torta

Michael Staber

Michael Kalcher

Wiesbauer Andreas

Kwan Siong Kenneth Choong

A multi-step analog-to-digital converter (ADC). The ADC includes a sampling circuitry, a comparator, a trimming circuitry, and a DC offset actuator. The sampling circuitry is configured to sample an input analog signal. The comparator is for comparing the input analog signal sample or a residual component of the input analog signal sample to a reference value in each step. The trimming circuitry is configured to receive at least one low-order bit (e.g., a least significant bit and/or a second-least significant bit) of digital binary bits of each input analog signal sample and average the low order bit over a plurality of input analog signal samples and generate a control signal for correcting an input DC offset of the comparator based on an average value of the low-order bits. The DC offset actuator is configured to correct the input DC offset of the comparator based on the control signal.

Method and system for digital background offset correction of a comparator in an analog-to-digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.

Successive approximation register analog-to-digital converter

A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift &#x394;&#x3c6;. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wand to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wto generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n&#x3e;1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

Multiphase signal generators, frequency multipliers, mixed signal circuits, and methods for generating phase shifted signals

A method includes post processing a plurality of temperature sensors grouped into a plurality of sets. For each set of the plurality of sets, a post-processing system coupled to corresponding temperature sensors receives a plurality output signals generated by the corresponding temperature sensors. For each set of the plurality of sets, the post-processing system computes values representing proportional to absolute temperature (PTAT) voltages and values representing internal reference voltages based on output signals generated by the corresponding temperature sensors. For each set of the plurality of sets, the post-processing system computes an average of the values representing the PTAT voltages and relative PTAT voltage variation coefficients. For each set of the plurality of sets, the post-processing system computes values representing corrected PTAT voltages using the relative PTAT voltage variation coefficients.

System and method for temperature sensing

In accordance with an embodiment, a method of operating an oversampled data converter having a switched-capacitor (SC) integrator includes operating the oversampled data converter in a gain calibration mode; applying a first voltage to a feedback port of the SC integrator to form a feedback voltage, and during a first clock phase the method further includes applying the first voltage to a first series capacitor via the input port when an output of the oversampled data converter is in a first state; applying a bypass voltage to the first series capacitor when the output of the oversampled data converter is an a second state and applying the first voltage to a second series capacitor via the feedback port with a polarity based on the output of the oversampled data converter, and during a second clock phase the method includes integrating charges of the first series capacitor and the second series capacitor.

Method of operation for an oversampled data converter

A switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signal at an output during a first phase of operation and an inverted version of the differential signal at an output during a second phase of operation. A driver amplifier component is configured to receive the non-inverted version of the differential signal at an input during the first phase of operation and the inverted version of the differential signal at an input during the second phase of operation. A sampling capacitor component is configured to sample the output of the driver amplifier component during the first phase of operation and the second phase of operation.

Cross-coupled input voltage sampling and driver amplifier flicker noise cancellation in a switched capacitor analog-to-digital converter

A modulator is configured to respond to input swings by providing a feedback voltage via a feedback path to compromise an increase in noise and distortion power with increasing signal power at signal levels exceeding a predetermined threshold. A digital-to-analog converter (DAC) generates a feedback voltage with a resistor string biased with a given current and switches as a function of an input value to mitigate the voltage swing at a summing node.

Very high dynamic-range switched capacitor ADC with large input impedance for applications tolerating increased distortion and noise at large input signal levels

A device for extracting a clock frequency underlying a data stream includes means for controlling a controllable oscillator, coarse-tuning means and fine-tuning means, wherein coarse-tuning means responds to a second data pattern present in the data stream and sets the oscillator coarsely based on its length. Fine-tuning means responds to temporally consecutive first data patterns present in the data stream with a higher accuracy in order to perform a fine tuning of the oscillator on the basis of the temporal length between the two first data patterns and on the basis of the number of clock cycles of the controllable oscillator occurring in this temporal length.

Method and device for extracting a clock frequency underlying a data stream

A multi-bit sigma/delta converter for converting an analog input signal into a digital output signal comprises a filter device for filtering the analog input signal which is added to a feedback signal to form an intermediate signal. An integrator device for integrating the filtered intermediate signal added to an inner feedback signal forms a quantizer input signal. A quantizer device quantizes the quantizer input signal to form the digital output signal. An inner feedback digital/analog converter is provided for converting the digital output signal directly into the inner feedback signal. A DEM device for performing dynamic element matching on the digital output signal and providing a matched digital signal is provided and a feedback digital/analog converter for converting the matched digital signal into the feedback signal is implemented.

Multi-bit sigma/delta converter

A digitally controllable oscillator includes an oscillation generation means and an oscillator control, wherein the oscillator control comprises two digital/analog converters whose output signals are combined by a combiner in order to generate an analog input signal into the oscillation generation means. The second digital/analog converter is implemented in order to provide, in response to a digital increment in its digital input signal, a difference in the output signal of the second digital/analog converter which is smaller than a difference in the output signal of the first digital/analog converter when the first digital/analog converter is pulsed with the digital increment in its digital input signal.

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Villach, Austria

Patrizia Greco