Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Patrik Larsson

Christopher John Nicol

Jean-Jacques Werner

Jian Yang

Per Magnusson

Meng-Lin Yu

Jay Henry O'Neill

Tracy C Denk

A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the present invention reduces the load on the clock and achieves reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder. The combination of a reduction of half of the flip-flops and a replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance and power and space consumption.

High-speed/low power finite impulse response filter

A system and method for echo and near end cross talk (E/N) cancellation in a communications system using a pair of FIR filter ICs, wherein a first FIR filter IC filters a plurality of low amplitude E/N signals and a first portion of a plurality of data bits of a plurality of high amplitude E/N signals, and a second FIR filter IC filters a second portion of the data bits of the high amplitude E/N signals which cannot be filtered by the first FIR filter IC. The output values from the two filters are then summed to produce the E/N cancellation signal. The present invention allows for the use of lower bit-resolution, lower power consumption, and less expensive filter ICs than conventional FIR filters implemented in a single IC.

System and method for filtering echo/NEXT signal interferrence

Multiported register files used for storing coefficients in adaptive FIR are improved upon by implementing a split memory architecture that has the ability to separately control the least significant bits and the most significant bits of coefficient values that are stored in the filter. When the filter is operated to use so-called &ldquo;burst mode&rdquo; updating, the updating circuitry of the filter can be disabled and only the most significant bits of the coefficients are read out from the multiported register file while the least significant bits remain unchanged. This conserves power without sacrificing precision, since only certain ones of the bits of the coefficients are used in the multiplication of the sample. In addition, when only the most significant bits of the coefficients are being cycled through the register filter, any changing bits are prevented from being supplied to the updating circuit, so that the updating circuit performs no computation at all, rather than performing one that is discarded. Advantageously, using such improved multiported register files, adaptive FIR filters can be constructed which operate with lower power consumption.

Multiported register file for burst mode coefficient updating

A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the load on the clock can be reduced, thereby achieving reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder. The combination of a reduction of half of the flip-flops and a replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance and power and space consumption.

Multiported register files for use in storing coefficients in adaptive FIR filters. incorporate computational ability, e.g., the ability to perform computation on coefficient values or derivatives thereof, or to control the operations performed thereon. For example, a multiported register file may incorporate an overflow/underflow detection and/or saturation unit. Also, the multiported register file may incorporate a special encoder to speed up the multiplication process, e.g., the so-called &ldquo;Booth&rdquo; encoder. Likewise, the multiported register file may incorporate a converter for changing the representation of the coefficients, e.g., a two's complement to sign-magnitude converter. All computation performed in the multiported register file is performed outside of the critical path of the filtering or of the coefficient updating. Using such improved multiported register files, adaptive FIR filters can be constructed which operate faster, and with lower power consumption.

Multiported register file for coefficient use in filters

A receiver, comprising an adaptive filter, performs blind equalization using a modified form of the constant modulus algorithm (CMA). This modified form of CMA is referred to as phase compensating CMA (PC-CMA). PC-CMA includes a phase-compensating term in the tap updating algorithm of the equalizer such that convergence to a straight constellation is achieved without the need of a rotator.

Phase-compensating constant modulus algorithm

In an Asymmetric Digital Subscriber Loop (ADSL) Discrete Multi-Tone (DMT) system, a DMT receiver uses, during start-up, an automatic gain control (AGC) element and a rotator element in place of a one-tap complex finite impulse response (FIR) filter.

Fast start-up in discrete multi-tone (DMT) based communications system

A frequency detector embodying the invention includes circuitry for comparing first (e.g., a reference) and second (e.g., a recovery clock) signals having first and second frequencies, respectively, and for producing an output signal having: (a) a first condition characterized as a &ldquo;dead zone&rdquo; when their frequency difference is within a predetermined frequency range; (b) a second condition when the frequency of the first signal is greater than that of the second signal by the predetermined range; and (c) a third condition when the frequency of the second signal is greater than that of the first by the predetermined range. Frequency detectors embodying the invention are suitable for use in frequency tuning systems. In one such system the output of a frequency detector is supplied to the input of a voltage controlled oscillator (VCO) for controlling the amplitude of the control voltage (Vc) applied to the VCO and the VCO output at which is produced the recovery clock signal (Ck) whose frequency is proportional to the amplitude of Vc. The frequency detector then functions to maintain the frequency of Ck within a predetermined frequency range. A system embodying the invention may also include a phase detector circuit responsive to the clock signal, Ck, and to a data input signal having a rate (ft) received from a transmitter for producing an output indicative of their phase difference, which output is also applied to the input of the VCO. In this embodiment the phase detector controls and locks the recovery clock signal to a frequency corresponding to the rate of the data input signals when the data rate is within the predetermined frequency range, without interference from the frequency detector.

Frequency detector circuits and systems

Multiported register files are employed to implement the input delays necessary for finite impulse response (FIR) filter operation. A multiported register file is a memory, typically small, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register tile may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port. At least one output of each multiported register file is coupled to the input of the next stage of the FIR filter, if any. In addition, each multiported register file feeds data from one output to the multiply-add portion of its associated stage of the FIR filter. When the introduction of at least one sample delay for a particular sample is necessary, the multiported register file storing that sample is operated to supply, as an output, data that was previously stored therein, regardless of any data currently being supplied to it as input. In contrast, when no sample delay is required for a particular sample to reach a particular multiported register file, the multiported register files in the path of that sample are operated in a lookthrough mode. The read and write addresses, as well as the write enable signals for each multiported register file may be supplied in a pipelined manner.

Filter structure and method

A capacitance multiplier network embodying the invention includes a first resistor, R1, connected between a first node and an intermediate node and a first capacitor, C1, connected between the intermediate node and a point of reference potential. A unity gain amplifier has an input connected to the intermediate node and its output is connected via a second resistor, R2, to the first node. The unity gain amplifier ensures that the voltage drop across the second resistor is equal to the voltage drop across the first resistor. The effective capacitance, Ce, of the network is equal to C1 times &lsqb;R1&plus;R2&rsqb;/R2. Thus, by making R1 larger than R2, Ce is much large than the capacitance of C1. The capacitance multiplier network is well suited for use in phase locked loop circuits and enables the integration of a very dense circuit on the same IC chip.

Apparatus and method for capacitance multiplication

In systems embodying the invention a voltage responsive circuit is used to generate a number of different clock signals having the same frequency, with each clock signal being delayed relative to any other clock signal by a certain delay which is a function of the amplitude of a control voltage applied to the voltage responsive circuit. The clock signals are multiplexed to enable any one of the different clock signals to be selected and to then be compared with a reference frequency signal for producing a gradually varying control voltage which is applied to the voltage responsive circuit. The different clock signals are suited for use in applications such as clock recovery and frequency synthesizer systems, where very little jitter is desired.

Digital phase selection circuitry and method for reducing jitter

A PLL circuit that includes a sampled phase detector, a filter and a voltage-controlled oscillator (VCO) is disclosed. The sampled phase detector compares an incoming reference signal, V,, and the output of the VCO, V,, to generate an error signal, I,, representing the phase difference between the reference signal, V,, and the VCO output, V,. The error signal, I,, is filtered by a low pass filter and applied to the VCO to produce an output signal, V,, that tracks the phase of the reference signal, V,. Jitter is reduced by reducing the delay between the sampled phase detector and the VCO. Delay is reduced by utilizing short current pulses, as opposed to the continuous charge-pump current produced by conventional sampled phase detectors. The sampled phase detector injects all the charge-pump current into the VCO at once, reducing the delay by up to half of a clock cycle. In a further implementation, the total delay in the feedback loop is reduced by applying a charge output current, I,, that is known to be required within a predefined period of time. An additional charge injection can be applied to the VCO each time the phase error value is zero, for the anticipated oscillation period until the next zero crossing. Thus, short pulses charge current, I,, are initially injected into the low pass filter following a zero crossing, to inject a similar charge for the estimated duration of the oscillation period, until the next zero crossing is predicted to occur.

Phase-locked loop (PLL) circuit containing a sampled phase detector with reduced jitter

A phase locked loop (PLL) includes a programmable frequency multiplier section and a programmable divide-by-N network connected in a feedback loop between an output and an input of the frequency multiplier. The frequency multiplier section includes programmable circuitry which is programmed to vary as a function of N to render the bandwidth of the PLL independent of the divider ratio 'N'. The frequency multiplier includes a charge pump circuit, a filter circuit and a voltage controlled oscillator (VCO) circuit with the programmable circuitry being formed in one of these circuits to render the bandwidth of the PLL independent of the divider ratio, whereby the bandwidth is increased and the jitter at the PLL output is decreased.

Phase locked loop (PLL) circuit

An extended frequency lock range is achieved in a phase-locked loop (PLL) circuit based on sampled phase detectors by introducing frequency feedback into the PLL circuit. At least one data sampler samples adjacent bits of incoming data, such as data bits D.sub.X and D.sub.Y, and an edge detector samples an edge, E, of the incoming data signal between the two data bits, D.sub.X and D.sub.Y. Sequence values '101' or '010' for the data bits D.sub.X, E and D.sub.Y, are not valid and indicate that the VCO is sampling the incoming data stream too slowly. When sequence values of '101' or '010' are measured by the sampled phase detectors, the frequency of the VCO output, V.sub.O, is known to be too low, and a constant current is preferably injected by the sampled phase detector into the PLL, until the frequency becomes too high, upon which a constant current of opposite polarity is applied. A PLL circuit having a frequency detector in combination with a biased phase detector is also disclosed, to ensure that the PLL can be locked. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. The VCO control voltage is initialized to a value below the lock-in voltage for a positive biased phase detector embodiment, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.

Phase-locked loop (PLL) circuit containing a frequency detector for

In systems embodying the invention X clock signals having the same frequency, with each clock signal having a different phase, are supplied to the inputs of a multiplexer whose output is connected to the input of an 'integer' frequency divider circuit; where X is an integer greater than 1. The mulitplexer is controlled to selectively supply different ones of the X clock signals to the frequency divider circuit for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.

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Matawan, NJ, United States of America

Patrik Larsson