Intel Corporation

Intel Mobile Communications Gmbh

Infineon Technologies Ag

Patrik Eder

Rolf H Kuehnis

Sankaran M Menon

Enrico David Carrieri

Albrecht Mayer

Helmut Reinig

Vladimir Todorov

Pradeep R Kumar

Markus Lyra

Kajetan Nuernberger

John Barstow

Michael Goedecke

Amit Badole

Abhiram Anantharamu

Alberto Ghiribaldi

Arumugam Vijayaraman

David Jennings

Richard Knight

In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.

System on a chip and method for operating a system on a chip

A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.

Systems, devices, and methods for connectors

Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Device, system and method to support communication of test, debug or trace information with an external input/output interface

An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.

Distributed timestamping in networks

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

Apparatuses and methods for a multiple master capable debug interface

One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.

Device throughput optimization for bus protocols

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

Embodiments of the present disclosure provide a method and apparatus for device testing via an optical interface. In one instance, the apparatus may comprise a test controller to operate a camera to generate an image to capture test data displayed on a screen of a device under test. The test controller may be configured to extract the test data from the image, analyze the test data, and generate feedback information for the device under test, based at least in part on a result of the analysis of the test data. The camera may be included in the apparatus and communicatively coupled with the test controller. Other embodiments may be described and/or claimed.

Using an optical interface between a device under test and a test apparatus

A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the functional unit. The trace resources include a network configuration having a plurality of nodes and a plurality of monitors, wherein each of the monitors is coupled to a node and is configured to determine trace information of a component. Further, a trace unit is coupled to the network configuration.

System having trace resources

A system includes an integrated circuit having a first component and a first unit. The first component is configured to generate a first trace information. The first unit is implemented in hardware and configured to generate a first time information based on a time of the generation of the first trace information and configured to generate a first data sequence including the first trace information and the first time information.

System and method for processing trace information

A method of protecting a password from unauthorized access and a data processing unit are provided. An embodiment of the method of protecting a password from unauthorized access comprises storing data representing at least a portion of a password in a memory, assigning the data to at least one of a plurality of instructions, storing the plurality of instructions as processor executable code in the memory, and preventing read-out of the processor executable code as data from the memory.

Growing community of inventors

Taufkirchen, Germany

Patrik Eder