Telefonaktiebolaget Lm Ericsson (publ)

Patrik Åberg

Magnus Templing

Stefan Runeson

Staffan Månsson

Victor Millnert

Bengt Wikenfalk

Ola Nilsson

A method for use in an automated wireless industrial system comprising a device configured to act as a control node and at least one field level device, wherein the method comprises: issuing a control communication; inserting at least one time delay (tk) to the control communication; noting the communication time (TCL) for the communication; comparing the time for communication (TCL) to an expected time for communication (TR); and determining if any of the at least one time delay (tk) should be adapted, and if so, adapting at least that time delay.

Latency management

A software monitoring arrangement () comprising a controller () configured to: a) receive a software code module (); b) introduce a plurality of probes () into the software code module (), each probe () being arranged to provide output () when executed; c) execute the software code module () generating an image log file () based on the output () of the probes (); d) provide image analysis () of the image log file (); e) provide an indication () of an expected behavior based on the image analysis (); f) receive an indication () of an actual behavior; g) compare the expected behavior as indicated by its indicator () to the actual behavior as indicated by its indicator (); and provide an alert () based on the comparison.

Software execution monitoring using neural networks

There is provided mechanisms for scheduling a task from a plurality of tasks to a processor core of a cluster of processor cores. The processor cores share caches. A method is performed by a controller. The method comprises determining group-wise task relationships between the plurality of tasks based on duration of cache misses resulting from running groups of the plurality of tasks on processor cores sharing the same cache. The method comprises scheduling the task to one of the processor cores based on the group-wise task relationships of the task.

Task scheduling

A method of a priority trainer of a many core processing system comprising a plurality of cores is disclosed. The many core processing system is configured to execute one or more computer jobs, and wherein the priority trainer comprises a controller, the method comprising:

Priority trainer for many core processing system

Disclosed herein is a trainer of a many core system comprising a plurality of cores for controlling resource utilization within the many core system, wherein the trainer comprises a controller configured to cause a task scheduler to add a first synthetic variable load () to at least one task thread comprising at least one task and to schedule the at least one task thread; cause a generic probe element () to set a plurality of probes configured to measure a real time requirement at a respective plurality of points within an execution of the at least one task thread; cause a training element () to calculate a real time slack measurement constant (RS) value based on the worst case timing for each of the plurality of probes and to select at least one of the plurality of probes, wherein the selected at least one probe has a worst case RS value, wherein the training element is further configured to calculate a system load constant (SL) value based on the worst case RS value; and to cause a resource manager to adjust at least one system parameter based on the at least one probe having the worst case RS value. Also disclosed is a method of a trainer and a computer program product.

Trainer of many core systems for adaptive resource control

A multi-processor system comprises a sending processor adapted to send a data message, a receiving processor adapted to receive the date message, and a memory unit associated with the receiving processor. The multi-processor system has a size-index table associated with the sending processor, and the sending processor is adapted to map a size of a payload portion of the data message to an index of the size-index table, and to send the data message containing the size, the index and the payload portion to the receiving processor. The multi-processor system also has mapping circuitry associated with the receiving processor. The mapping circuitry is adapted to the map the index contained in the data message received from the sending processor to a pointer, wherein the pointer is associated with a buffer of the memory unit. The receiving processor is adapted to write the payload portion of the received data message to the buffer as indicated by the pointer. A receiving processor adapted to be comprised in a multi-processor system, an electronic apparatus comprising a multi-processor system and/or a receiving processor are also described as well as a method of receiving a data message at a processor.

System, processor, apparatus and method for inter-processor communication

A method for determining the size of each of a predetermined number of memory frames to be allocated for storing data blocks in a memory, and a processing device for implementing the method. The method comprises determining a data block size distribution for at least one set of data blocks. A data block size of the data block size distribution is eliminated iteratively until the number of data block sizes corresponds to the number of sizes of the memory frames. The data block sizes to merge are selected by means of a slack prediction algorithm. The sizes of the memory frames are determined as the data block sizes of the distribution which remain after the elimination.

Growing community of inventors

Södra Sandby, Sweden

Patrik Åberg