Cypress Semiconductor Corporation

Patrick Zicolello

Christopher John Petti

Andrew J Walker

Steven Sanders

Cathal G Phelan

Ashish Pancholy

Ke-Cai Zeng

Peter H Voss

Brett Alan Spurlock

Edward D Huber

Vincent Uy

Jeff Watt

Steven Cummins

A test system and method are provided for testing in parallel radiant output of multiple light emitting devices. Generally, the method involves: (i) providing a system having a master, calibrated power meter (CPM), a source transfer standard (STS), and multiple secondary, test site power meters (TSPMs); (ii) determining a relationship between electrical power supplied to the STS and a radiant output therefrom as measured by the CPM; (iii) calibrating the TSPMs using the STS and the relationship between the power supplied to the STS and the radiant output therefrom as determined by the CPM; and (iv) positioning the devices undergoing test on a fixture of the test system and positioning the fixture relative to the TSPMs to test radiant outputs of the devices. Preferably, the TSPMs are calibrated by exposing each to the STS at a known power, determining a difference between the radiant output measured by the CPM and TSPM, using this difference as an offset that is added to the a signal from the TSPM to provide a corrected radiant output for the device under test. Other embodiments are also disclosed.

Multi-site optical power calibration system and method

Input device

A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

Method and apparatus to prevent latch-up in CMOS devices

Growing community of inventors

Santa Clara, CA, United States of America

Patrick Zicolello