Sharp Kabushiki Kaisha Corporation

Sharp Life Science Corporation

Patrick Zebedee

Gareth John

Benjamin James Hadwen

Sunay Shah

Michael James Brownlow

Harry Garth Walton

Adrian Marc Simon Jacobs

Jason Roderick Hector

Jaganath Rajendra

Jeremy Lock

Kazuhiro Maeda

Yasushi Kubota

Hajime Washio

Graham Andrew Cairns

Lesley Anne Parry-Jones

Allan Evans

Stephen Day

Gareth Nicholas

Tim Gasser

Olivier Karim Abed-meraim

A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

Shift register and active matrix device

A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors () are provided for selectively isolating the charge storage node from a first voltage input (,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node () at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (). The first transistor forms part of the voltage follower circuit.

Charge storage circuit for a pixel, and a display

A pixel circuit for a display includes a pixel storage node for storing and presenting a pixel voltage to a pixel display element, a cell storage node for storing the data on the pixel storage node, and a first storage capacitor and a second storage capacitor each including a first electrode and a second electrode. The first electrode of the first storage capacitor is operatively coupled to the pixel storage node and the first electrode of the second storage capacitor operatively coupled to the cell storage node. The second electrode of the first and second storage capacitors is operatively coupled to a respective different one of first and second independent voltage signal lines. The pixel circuit further includes a pixel write circuit configured to write the pixel voltage to the pixel storage node during a data write cycle, and to provide respective voltage signals to the first and second independent voltage signal lines, each of the respective voltage signals being changed during the data write cycle in order to increase or reduce the pixel voltage.

Display device for active storage pixel inversion and method of driving the same

A pixel circuit is disclosed that includes a video mode, a memory mode and an inversion mode of operation. The pixel circuit includes a pixel storage node for storing data to be output by a liquid crystal cell, a pixel write circuit configured to receive display data and provide the display data to the pixel storage node for storage thereon. Further, the pixel circuit includes a hold circuit operatively coupled to the pixel write circuit and configured to minimize leakage of charge from the pixel storage node through the pixel write circuit, and an internal inversion circuit operatively coupled to the hold circuit and the pixel storage node and configured to invert a voltage of the data stored on the pixel storage node and a voltage applied to a liquid crystal cell that receives data stored on the pixel storage node.

An array element circuit with an integrated impedance sensor is provided. The array element circuit includes an array element which is controlled by application of a drive voltage by a drive element; writing circuitry for writing the drive voltage to the drive element; and sense circuitry for sensing an impedance presented at the drive element.

Array element circuit and active matrix device

A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively.

Static random-access cell, active matrix device and array element circuit

A serial-to-parallel converter which includes n input latching elements; k intermediate latching elements, and n output latching elements configured to sample outputs of the k intermediate latching elements and a remaining (n&#x2212;k) input latching elements of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n&#x3e;k.

Serial-to-parallel converter, and display device incorporating the same

An active-matrix device is provided which includes a plurality of array element circuits arranged in rows and columns; a plurality of source addressing lines each shared between the array element circuits in corresponding same columns; a plurality of gate addressing lines each shared between the array element circuits in corresponding same rows; a plurality of sensor row select lines each shared between the array element circuits in corresponding same rows, wherein each of the plurality of array element circuits includes: an array element which is controlled by application of a drive voltage by a drive element; writing circuitry for writing the drive voltage to the drive element, the writing circuitry being coupled to a corresponding source addressing line and gate addressing line among the plurality of source addressing lines and gate addressing lines; and sense circuitry for sensing an impedance presented at the drive element, the sense circuitry being coupled to a corresponding sensor row select line; and a row driver and a column driver.

In one embodiment of the present invention, a display for receiving m-bit display data includes a display driver including a switched capacitor digital/analogue converter including an n-bit input, where m is not greater than n. The upper plates of the capacitors of the switched capacitor digital/analogue converter may be connected, in the zeroing phase, to one of a plurality of reference voltages. The choice of which reference voltage is connected to the upper plates of the capacitors of the switched capacitor digital/analogue converter in the zeroing phase is independent of the input n-bit digital code, and is determined by a signal internal to the display. The output voltage range from the converter in a decoding phase may be a first range in which output voltages are above and below one reference voltage or it may be a second range in which output voltages are above and below another reference voltage, depending on which reference voltage was selected in the preceding zeroing phase.

Display

In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

Drive circuit, a display device provided with the same

In one embodiment of the present invention, a multiple phase pulse generator includes n stages, where each stage includes a first sub-stage and a second sub-stage. The first sub-stage includes a first memory element and the second sub-stage includes a second memory element. The first memory element of each stage is arranged to be set by the preceding stage. The first sub-stage is arranged to supply a stage output pulse while the first memory element is set. The second memory element is arranged to be set by the stage output pulse. The second sub-stage is arranged to hold the first memory element reset after the stage output pulse while the second memory element is set.

Multiple phase pulse generator

A display device includes a first layer having an optically active display portion, a second layer including a photovoltaic element, and a third layer including electronics operatively coupled to the first layer, wherein the electronics are configured to drive the optically active display portion. Further, the second layer is arranged between the first and third layers.

Integrated display and photovoltaic element

A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.

Digital logic circuit, shift register and active matrix device

A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n&#x2212;1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

Digital to analogue converter

A digital-to-analogue conversion arrangement is disclosed which includes first and second groups of the same number of bi-directional bufferless digital-to-analogue converters. The output of at least one converter in each group is connected to a respective capacitive load (C, C). During a calibration phase of operation the converter inputs receive first and second different codes representing the same output level. The arrangement also includes a respective switched capacitor network connected to each converter output, a comparator for comparing the output voltages of the first and second groups, and a control circuit. The control circuit controls the capacitor networks in response to the comparator so as to make the output voltages of the first and second groups substantially equal.

Growing community of inventors

Oxford, United Kingdom

Patrick Zebedee