Photonic Technologies (shanghai) Co., Ltd.

Fudan University

Patrick Yin Chiang

Rui Bai

Xuefeng Chen

Juncheng Wang

Xin Wang

Tao Xia

Wenjun He

Shang Hu

Wenzong Pan

Zhichun Wang

Yuanxi Zhang

Ming Lu

Shenglong Zhuo

Jianxu Ma

Zhongkai Wang

The disclosure relates to a pulsed laser driver that utilizes a high-voltage switch transistor to support a high output voltage for a laser, and a low-voltage switch transistor that switches between an ON state and an OFF state to generate a pulsed current that is supplied to the laser to generate an output pulsed laser signal. The pulsed laser driver switches the low-voltage switch transistor between the ON state and the OFF state according to an input pulsed signal such that the output pulsed laser signal is modulated according to the input pulsed signal. The pulsed laser driver also utilizes a feedback control module to control the gate terminal voltage of the high-voltage switch transistor to improve the precision of the output pulsed laser signal.

Pulsed laser driver

An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.

Method and apparatus for built-in self-test of CDR and non-CDR components with an on substrate test signal generator

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Clock and data recovery circuit

Frequency detector, and clock and data recovery circuit including the frequency detector

Non-transitory machine readable medium for clock recovery

Apparatus and method for clock recovery based on non-non return to zero (non-NRZ) data signals

Frequency detector for clock recovery

Apparatus and method for clock recovery

A clock and data recovery (CDR) circuit employing zero-crossing linearizing (ZCL) technique. The circuit including a voltage controlled oscillator (VCO), an inject-locked divider (ILD), a variable delay unit, a linearized loop, a bang-bang loop, and a loop filter (LP). The differential clock generated by VCO passes through ILD for frequency dividing and variable delay unit to generate 8-phase clocks. Then using these clocks, the PDs over-sample the input data, followed by synchronization and logic operation to control the CPs output current pulses. These currents filtered by LP control the VCO to finish the loop. The circuit recovers 4 channel data and corresponding clocks of the input with low power broken-down and preferable jitter performance and locking property.

Growing community of inventors

Shanghai, China

Patrick Yin Chiang