Aspec Technology, Inc.

Patrick Yin

Craig S Thrower

A system and method is provided which generates integrated circuits for integrated circuits that are portable from process to process. Information generated from an integrated circuit manufactured on a first process is utilized in combination with the parameters of a subsequent manufacturing process to obtain an integrated circuit based upon that second manufacturing process. Through this system and method a particular integrated circuit design is portable from process to process.

Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another

An improved output driver circuit is disclosed which can be utilized when a plurality of voltage potentials are present. The output driver circuit comprises a first pull-up transistor coupled to a first voltage potential, a second pull-down transistor coupled to a second voltage potential, and a pad member coupled to the first pull-up and second pull-down transistor. The driver circuit further includes a circuit means which is coupled to the pad member and the first pull-up transistor. Accordingly, through this arrangement, the circuit substantially reduces the leakage through the first pull-up transistor when the pad member is coupled to a third voltage potential. An output driver circuit in accordance with the present invention, can be utilized in an integrated circuit environment where multiple voltages such as 3.3 volts and 5 volts are present and the output driver circuit will operate effectively because the leakage path normally associated with such circuits is substantially minimized.

Low leakage output driver circuit which can be utilized in a

A cell architecture for mixed signal applications is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a transistor arrangement in which substrate taps are located adjacent to the transistor pairs. This provides for a more 'symmetric' cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The cell architecture includes a substrate tap area that allows for the accommodation of a plurality of electrically isolated metal lines.

Cell architecture for mixed signal applications

A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more 'symmetric' cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The architecture further includes a plurality of probe lines that are located within the architecture to facilitate testability of the outputs of the architecture.

Symmetrical multi-layer metal logic array with extension portions for

A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more 'symmetric' cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Symmetrical multi-layer metal logic array with continuous substrate taps

A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more 'symmetric' cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

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Fremont, CA, United States of America

Patrick Yin