Koninklijke Philips Corporation N.V.

Nxp B.v.

Patrick Willem Hubert Heuts

Hendrik Boezen

Peter Fuhrmann

Aloysius Johannes Maria Boomkamp

Franciscus Johannes Klosters

Joris Rudolf Beverloo

Hendrik Bernard Heule

Wolfgang Otto Budde

Manfred Bruno Zinke

Robert Mores

Jozef Laurentius Wilhelmus Kessels

Adrianus Marinus Gerardus Peeters

Abraham Klaas Van Den Heuvel

Stefan Gerhard Erich Butselaar

Ruurd Anne Visser

Peter Michael Buehring

Martinus Bredius

Harm Gerwin Joan Voss

Egon Joehnk

Maarten Teunis Visser

A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.

Data processing apparatus that processes incoming bits

The invention describes a method for the monitoring and management of data traffic in a communication system with several communication nodes which communicate via interfaces monitored by a bus monitor, comprising the following steps: a) provision of a predefined communication time schedule for all communication nodes, b) initialization of the bus monitor, c) synchronization of the communication time schedule of the bus monitor with the predefined communication time schedule executed by the communication nodes in a distributed arrangement, the synchronization taking place on the basis of activities observed at the interfaces, d) monitoring of the activities of the communication nodes by the bus monitor, e) comparison of the activities with the predefined communication time schedule, and f) deactivation of the interface for any communication node for which an activity not compatible with the predefined communication time schedule has been detected. A circuit arrangement and its use are also described.

Method and circuit arrangement for the monitoring and management of data traffic in a communication system with several communication nodes

A data processing apparatus receives a message containing a sync break interval with a unique bit pattern and a sync field interval identified by the sync break interval. A timing property of the sync field interval specifies the length of bit periods of the message. A clock source circuit supplies a sampling clock signal to define time points for sampling bits from the message. The clock source circuit adapts a frequency of the sampling clock signal to the timing property of the sync field interval. The clock source circuit searches for potential sync break intervals that match the unique bit pattern for a range of bit period values and verifies for each potential sync break interval whether the sync field interval identified by that potential sync break interval specifies a bit period with a duration so that the sync break interval matches the unique pattern for the specified bit period, as a condition prior to supplying the sampling clock signal at the adapted frequency specified by the sync field interval identified by the potential sync break interval. Supply of sampling clock signals is preferably suppressed after an end of a preceding message until said condition is met.

Data processing apparatus that identifies a communication clock frequency

The communication bus system comprises a plurality of node circuits (-) and a relay circuit () coupling the node circuits (-). The relay circuit () has a transceiver circuit () for relaying messages () between the node circuits (-) in a normal mode. The transceiver circuit () is powered down in a sleep mode. A detector circuit () detects an incoming message () when the relay circuit () is in a sleep mode. A mode control circuit () powers up the transceiver () in response to detection of an incoming message (). Steps are taken that ensure, in the normal mode, that messages () will not be relayed in unreadable form. The mode control circuit () is arranged to cause the transceiver () to relay a remainder () of the incoming message () after power up. In an embodiment the power needed to transmit the remainder () of the message () is drained from a capacitor () in the power supply () before the power supply () controls the power supply voltage in the normal mode. In another embodiment the detector circuit () temporarily controls the direction of operation of the transceivers () at the start of the normal mode instead of further detectors (-) that normally control the direction of operation in the normal mode.

Communication bus system operable in a sleep mode and a normal mode

The invention relates to a network comprising a plurality of network nodes and one star node, which star node is provided for the direct coupling of at least two network nodes. The star node comprises a plurality of star interfaces which are assigned to at least one network node and which comprise each an activity detector for detecting activities in the message signal coming from the assigned network node and for transferring the message signal from the assigned network node to the other star interfaces or from another star interface to the assigned network node in dependence on at least one activity.

Activity detection in a star node with a plurality of coupled network nodes

A CAN communication line is operated whilst detecting a ground level shift on the communication line through storing a data element indicative for the shift. In particular, a current line voltage level is compared to a standard level, and a thresholded version of the comparison is fed to a storage element that is triggered by a local transmission indicator signal. Then a ground shift sample bit from the storage element is outputted.

Station and method for operating a CAN communication line

An integrated circuit according to the invention comprises at least a first and a second circuit ( resp.) and a first and a second signal path ( and resp.) between the first and the second circuit. The first and the second signal path each comprise a selection element ( ) which has a first input ( ) coupled to the first circuit ( ), and a second input ( ). The selection element ( ) has an output (30 ) coupled to the second circuit ( ). The second input ( ) of the selection element ( ) of the second signal path ( ) is coupled to a memory element ( ). The output ( ) of the selection element ( ) of the first signal path ( ) is coupled to an input ( ) of the memory element ( ).

Integrated circuit

A fault tolerant air bag system needs a floating supply, which supply conventionally is made by means of a DC-DC converter with a transformer. By splitting the main energy reserve capacitor ( ) into two capacitors ( ), and coupling one of the capacitors ( ) to the other ( ) by means of switches ( ) which open during a crash, no transformer is needed any more.

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Nijmegen, Netherlands

Patrick Willem Hubert Heuts