Telefonaktiebolaget Lm Ericsson (publ)

Advanced Micro Devices Corporation

Patrick Wang

Edward Ho

Michael Feng

Ranjit Joseph Rozario

Edmund C Chen

Thomas C Yip

Sun Den Chen

Stephen Chow

Barry Alan Hoberman

Daniel Christian Biederman

Ramanathan Lakshmikanthan

Brian Alleyne

David Jonq Wang

Ravi Tangirala

Stuart T Auvinen

Sunden Chen

Afshin Ganjooi

Peter Klikovits

Srivi Dhruvanarayan

A network device in a network is provided that is configured to implement a process for modifying a timestamp in a packet that is a timing protocol packet. The timing protocol packet is encapsulated by a user data protocol (UDP) datagram, where the modified timestamp is written into the packet, but does not require a checksum of the UDP datagram to be changed. The process includes receiving a packet including a first timestamp over the network, receiving the first timestamp from the packet and a second timestamp to be written to the packet, and determining a third timestamp that is a modification of the second timestamp to be written to the packet, the third timestamp having least significant bits modified from the second timestamp such that the checksum of the UDP datagram is unchanged. The process writes the third timestamp into the packet and transmits the UDP datagram to the network.

Checksum friendly timestamp update

A method is performed in a requester device that is coupled with a responder device by a serial interface. The method is one of selecting an approach to handle an error in a request-response communication between the requester and responder devices over the serial interface. The method includes transmitting a request packet, of the request-response communication, over the serial interface, based on a request from an application that is executing on a logical processor. The method includes reporting the error in the request-response communication to an application-layer module. The method includes selecting an error handling approach, of a plurality of error handling approaches, which is to be used to handle the error, with the application-layer module.

Reporting errors on serial interfaces to application layers for flexible error handling approach selection

Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

On-chip packet cut-through

A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

Hierarchical pipelined distributed scheduling traffic manager

A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.

RAM based FIFO memory half-full detection apparatus and method

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Palo Alto, CA, United States of America

Patrick Wang