International Business Machines Corporation

Patrick W Gallagher

James Wilson Bishop

Gregory Robert Klouda

Stefan P Jackowski

Robert D Siegl

Steven Lee Gregor

Mark Louis Ciacelli

Charles Embrey Carmack, Jr

Stephen M Reeve

In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.

Error windowing for storage subsystem recovery

A hierarchical cache system comprises a plurality of first level cache subsystems for storing data or instructions of respective CPUs, a higher level cache subsystem containing data or instructions of the plurality of cache subsystems, and a main memory coupled to the higher level cache subsystem. A page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory, by storing the data into the main memory without copying previous contents of a store-to address of the request to the higher level cache subsystem in response to said request. Also, the page mover invalidates the previous contents in the higher level cache subsystem if already resident there when the CPU made the request. A buffering system within the page mover comprises request buffers and data segment buffers to store a segment of predetermined size of the data. When all of the request buffers have like priority and there are fewer request buffers that contain respective, outstanding requests than the number of data segment buffers, the page mover means allocates to the request buffers with outstanding requests use of the data segment buffers for which there are no outstanding requests.

Hierarchical computer cache system

In a computer system in which conflicting requests for resources are prioritized, a programmable priority determination method and system. Relative priority between competing sources or requests is represented by a control word (priority code). The control word includes bits identifying the highest priority source, and rotation and skip bits determining the order or priority among the other sources. The control word is used to pre-set a priority circuit which then selects from among competing resource requests based on the priority represented by the control word. Relative priority between the sources can be changed during operation of the computer system by creating a new control word and applying it to the priority circuit.

Programmable priority and selective blocking in a compute system

A multilevel cache buffer for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.

Shared two level cache including apparatus for maintaining storage

In a computer system, programmable priority as well as selective blocking in order to make selection between instructions and commands which require the use of common resources.

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Vestal, NY, United States of America

Patrick W Gallagher