Intel Corporation

Infineon Technologies Ag

Apple Inc.

Patrick Torta

Lukas Doerrer

Francesco Conzatti

Luca Sant

Andrea Fant

Marco Bresciani

John G Kauffman

Udo Schuetz

Mario Motz

Kameran Azadet

Edwin Thaller

Matteo Camponeschi

Patrizia Greco

James M Yoder

Yu-Shan Wang

Ramani Tatikola

Georg Weber

Wee Liew

Claus Kropf

A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Chip-to-chip interface of a multi-chip module (MCM)

An active filter and an analog-to-digital converter (ADC) configured to suppress out-of-band peaking. An active filter may include an active device configured to provide a power gain to an input signal, a feedback network configured to connect an output of the active device to an input of the active device, and an input impedance network configured to couple the input signal to the input of the active device. A combination of the feedback network and the input impedance network is configured to provide frequency response properties of the active filter such that a frequency domain signal transfer function of the active filter has a constant in numerator.

Active filter configured to suppress out-of-band peaking and an analog-to-digital converter using the same

Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.

Offset system and method for multi-bit digital-to-analog converters

Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

Sigma-delta analog-to-digital converter including loop filter having components for feedback digital-to-analog converter correction

Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first 'pre-modulation' tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second 'modulation' phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Configurable system for cancellation of the mean value of a modulated signal

This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents.

Input common mode circuit for a fully differential amplifier

Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component.

Square wave signal component cancellation

A multi-bit sigma/delta converter for converting an analog input signal into a digital output signal comprises a filter device for filtering the analog input signal which is added to a feedback signal to form an intermediate signal. An integrator device for integrating the filtered intermediate signal added to an inner feedback signal forms a quantizer input signal. A quantizer device quantizes the quantizer input signal to form the digital output signal. An inner feedback digital/analog converter is provided for converting the digital output signal directly into the inner feedback signal. A DEM device for performing dynamic element matching on the digital output signal and providing a matched digital signal is provided and a feedback digital/analog converter for converting the matched digital signal into the feedback signal is implemented.

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Villach, Austria

Patrick Torta