Intel Corporation

Patrick Theofanis

Rishabh Mehandru

Stephen M Cea

Aaron D Lilak

James M Blackwell

Marie Krysak

Lauren Doyle

Matthew V Metz

Patrick R Morrow

Tanay Gosavi

Dmitri E Nikonov

Uygar E Avci

Kevin Lai Lin

Kevin O'Brien

Kelin J Kuhn

Seiyon Kim

Florian Gstrein

Chia-Ching Lin

Shriram Shivaraman

Cory E Weber

Ashish Verma Penumatcha

Eungnak Han

Carl H Naylor

Chelsey Dorow

Kirby Maxey

Chytra Pawashe

Sudarat Lee

Michael Robinson

Jorge A Munoz

Brian Zaccheo

Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

Transistors with monocrystalline metal chalcogenide channel materials

Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

EUV patterning methods, structures, and materials

Chain scission resist compositions suitable for EUV lithography applications may include monomer functional groups that improve the kinetics and/or thermodynamics of the scission mechanism. Chain scission resists may include monomer functional groups that reduce the risk that leaving groups generated through the scission mechanism may chemically corrode processing equipment.

Chain scission resist compositions for EUV lithography applications

An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polymer with an electrically conductive material.

Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability

An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.

Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing

Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

Magnetic nanomechanical devices for stiction compensation

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Pasadena, CA, United States of America

Patrick Theofanis