Micron Technology Incorporated

Patrick T Caraher

Michael Richard Spica

Gary D Hamor

João Elmiro Da Rocha Chaves

Donald Shepard

Michael B Danielson

A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.

Intelligent memory device test rack

A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.

Power management component for memory sub-system voltage regulation

A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.

A device under test for performing built-in self-tests to determine the functionality of one or more components of the device under test is described. The device under test includes a storage location to store a set of tests for testing the device under test; a data generator to generate a test pattern based on a test in the set of tests; a transmission unit to transmit the test pattern to a test system; a receiver unit to receive a set of loopback signals from the test system, wherein the set of loopback signals represent the test pattern; and a data checker to determine success or failure of the device under test based on the set of loopback signals.

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Niwot, CO, United States of America

Patrick T Caraher