Other

Xilinx, Inc.

Patrick T Bever

Brian D Erickson

Barry Wong

A rider support assembly for a bicycle, motorcycle or other multi-wheeled vehicle that utilizes a harness to suspend the rider from a support frame that is attached to a ball-type mounting structure. The support harness includes straps or a sling that is secured to the rider's torso and/or legs. A base section of the support frame includes a connecting structure (e.g., a socket) that is movably connects to and supported by the mounting structure such that the support frame can be pivoted in any direction by the rider during operation. A flexible spine extends upward along the rider's back and is secured to the rider's upper body by the support harness. An optional mounting structure pivots relative to the vehicle to facilitate a relatively stiff spine that supports the rider when sitting upright or leaning back.

Rider support assembly for multi-wheeled vehicle

A programmable logic device (PLD) including a non-volatile memory array for persistently storing configuration data, and a volatile memory array for temporarily storing the configuration data and controlling the various logic resources of the PLD to perform a user's logic operation. When the PLD is reset, an addressing circuit causes a column of non-volatile memory cells to transmit configuration data values to a corresponding column of volatile memory cells on a series of write lines. To verify that a configuration data value is successfully written from each non-volatile memory cell to a corresponding volatile memory cell, the data value transmitted on each write line is compared with the stored data value transmitted from each volatile memory cell on a corresponding read line. A control signal is generated when all of the data values transmitted on the write lines are equal to stored data values transmitted on corresponding read lines, thereby indicating that the configuration data values are successfully transferred to the column of volatile memory cells. The control signal is used to increment the address circuit, thereby addressing a next sequential column of non-volatile memory cells and associated volatile memory cells. Normal PLD operation is initiated when all configuration data is transferred.

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Santa Clara, CA, United States of America

Patrick T Bever