Cadence Design Systems, Inc.

Evans & Sutherland Computer Corporation

Cadance Design Systems, Inc.

Patrick Scaglia

Patrick Charles McGeer

Szu-Tsung Cheng

Alexander Saldanha

Carole Dulong

Jean-Yves Leclerc

Michael Jude Meyer

A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

Latch inference using dataflow analysis

A hardware design language V&plus;&plus; is described. V&plus;&plus; provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V&plus;&plus; each program is directly interpreted as a network of communicating finite state machines. The composition of two V&plus;&plus; programs is a V&plus;&plus; program, with well-defined, deterministic semantics.

Hardware design language for the design of integrated circuits

A task status word (TSW) is created for each task indicating, the instant location of the task, its priority and a record of synchronizing signals. Task status words are accessible from an addressable memory section for delivery to a TSW register. From the TSW register, a selected TSW effects control functions to synchronize tasks in different processors or computational units as well as input-output processors. A physical memory manager locates TSWs in response to signals, then checks the location of the task and the nature of the signal to determine signal routing to a processor. If a task is not in a processor, an interrupt manager resolves priority and signal significance indicated by the TSW to determine an interrupt.

Multiprocessor task scheduling system

In a pipeline computer, current instructions executed in sequence are monitored for conditional and unconditional branch commands, as well as the readiness of condition codes, the meeting of branch conditions and split commands. A branch command initiates an interval of delay which affords prefetching target instructions while using pipeline contents to prevent a pipeline break and avoid lost time. Detection of a branch command actuates a register to store a sequence of target instructions. Unless a branch command is conditional, subsequent detection (delayed) of a split command shifts the stored target instructions into operation as the current instructions. For a conditional branch command, a jump or split to the target instructions is performed only if the condition is met. Otherwise the current instruction sequence is restored pending another branch command. Dual instruction registers, program counters and address registers alternate to accommodate branch jumps with considerable time savings by effective programming.

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Saratoga, CA, United States of America

Patrick Scaglia