Texas Instruments Corporation

Tektronix, Inc.

Xilinx, Inc.

Patrick Satarzadeh

Venkatesh Srinivasan

Gregory A Martin

Charles Sestok

Marco Corsi

Pirooz Hojabri

Karen Hovakimyan

Baher S Haroun

Arthur John Redfern

Hongtao Zhang

Zhaoyin D Wu

Geoffrey Zhang

Joshua J O'Brien

John J Pickerd

Kun Shi

Daniel G Knierim

Fernando Alberto Mujica

Barton T Hickman

Yu Xu

Victoria Wang

Victoria W Limetkai

Hungming Chang

Khadar Baba Shaik

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Integrated communication link testing

A test and measurement device having a signal source, including an impairment generator configured to output an impairment and a waveform synthesizer. The waveform synthesizer receives an input digital signal to be synthesized, receives the impairment, and synthesizes a synthesized digital signal based on the input digital signal and the impairment. The test and measurement instrument also includes a fixed sample rate digital-to-analog converter configured to receive a clock signal and the synthesized digital signal and output an analog signal.

Real-time jitter impairment insertion for signal sources

A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.

Digital signal processing waveform synthesis for fixed sample rate signal sources

Disclosed are systems and methods related to a noise reduction device employing an analog filter and a corresponding inverse digital filter. The combination and placement of the filters within the systems aids in reducing noise introduced by processing the signal. In some embodiments, the combination of filters may also provide for increased flexibility when de-embedding device under test (DUT) link attenuation at higher frequencies. Further, the filters are adjustable, via a controller, to obtain an increased signal to noise ratio (SNR) relative to a signal channel lacking the combination of filters. Additional embodiments may be disclosed and/or claimed herein.

Noise reduction in digitizing systems

In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.

Signal loss detector

Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Method for calibrating a pipelined continuous-time sigma delta modulator

A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit coupled to receive the input signal; and a calibration circuit coupled to the receiver, the calibration circuit having an input for receiving the input signal; an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.

Circuits for and methods of receiving data in an integrated circuit

In a method for channel adaptation, an analog input signal is received with a bimodal receiver via a communications channel. The analog input signal is converted to a digital input signal with an analog-to-digital converter of a digital receiver of the bimodal receiver. Channel coefficients are detected for the digital input signal associated with the communications channel. The channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized digital output signal from the digital input signal. It is determined whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number. A switch from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver is made to provide the equalized digital output signal for the analog input signal.

Channel adaptive receiver switchable from a digital-based receiver mode to an analog-based receiver mode

Pipelined continuous-time sigma delta modulator

Method for calbrating a pipelined continuous-time sigma delta modulator

A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Excess loop delay compensation for a continuous time sigma delta modulator

An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.

Pipelined ADC inter-stage error calibration

A method for converting a sampled analog signal into digital is provided. An input signal is sampled at a sampling instant to generate a sample voltage. A first current is then applied to a node to change a voltage on the node, and a first interval to change the voltage on the node to a reference voltage from the sample voltage using the first current is determined. A second current is then applied to the node to change a voltage on the node prior to a subsequent sampling instant, and a determination of a second interval to change the voltage on the node to the reference voltage from the sample voltage using the second current is made.

Growing community of inventors

Addison, TX, United States of America

Patrick Satarzadeh