Mellanox Technologies, Ltd.

Tilera Corporation

Massachusetts Institute of Technology

Patrick Robert Griffin

Anant Agarwal

Carl Ramey

David M Wentzlaff

Chyi-Chang Miao

Bruce Edwards

Christopher D Metcalf

Walter Lee

Mathew Hostetter

Mark B Rosenbluth

Matthew Mattina

Ian Rudolf Bratt

Christopher J Jackson

Richard Schooler

Liewei Bao

Kenneth M Steele

Shane Bell

John A Amann

Richard Conlin

Ben Harrison

Kevin Joyce

Christine Deignan

Chris Metcalf

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Computing in parallel processing environments

Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

Programming in a multiprocessor environment

Coupling a device to a multicore computing system that includes multiple cores that each include a processor includes sending messages to access memory coupled to at least one of the multiple cores, the memory having an address space, and the messages including a virtual address. An interface is provided for coupling the device to the multicore computing system in a shim that: transmits or receives messages on the communication network among the processors to or from the coupled device, and translates virtual addresses to physical addresses of the address space in response to receiving the messages over the communication network that include a virtual address.

Configurable device interfaces

Receiving data at a first device transferred from a second device includes: storing a starting address with respect to a memory address space for a memory of the first device in a storage location within the first device. A request is received at the first device to transfer one or more data values from the second device, the request including a target address with respect to a communication channel address space for a communication channel between the first device and the second device. The second device determines whether the target address corresponds to a reserved address value designated as an indicator of a transfer to a memory address beyond the communication channel address space. The one or more data values are transferred from the second device to the first device according to the stored starting address if the target address does correspond to the reserved address value, or the one or more data values are transferred from the second device to the first device according to the target address if the target address does not correspond to the reserved address value.

Memory-mapped data transfers

The present invention provides a method and system for managing virtual addresses of a plurality of processes corresponding to an application. The method comprises designating a first set of ranges of virtual addresses to the plurality of processes, wherein the virtual addresses of the first set of ranges map to a memory region shared among the plurality of processes. Further, the method comprises designating a second set of ranges of virtual addresses to the plurality of processes, wherein the virtual addresses of the second set of ranges map to a memory region independently used by a process of the plurality of processes. Furthermore, the method comprises adding or removing virtual address ranges from one of the first set of ranges and the second set of ranges based on requirements of the application, wherein the addition or removal is performed in virtual addresses of the plurality of processes.

Method and system for managing virtual addresses of a plurality of processes corresponding to an application

An the integrated circuit comprises a plurality of processor cores interconnected by an interconnection network. A method for generating instructions to be executed in the integrated circuit comprises accepting a plurality of programs, at least some of the programs including one or more communication operations to communicate with other programs; mapping each program to one or more of the processor cores; determining correspondence among communication operations in the programs; and mapping communication for corresponding communication operations to resources associated with the interconnection network.

Mapping communication in a parallel processing environment

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Brookline, MA, United States of America

Patrick Robert Griffin