Soitec

S.o.i.tec Silicon on Insulator Technologies

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Patrick Reynaud

Sébastien Kerdiles

Daniel Delprat

Oleg Kononchuk

Walter Schwarzenbach

Ludovic Ecarnot

Emmanuel Rolland

Eric Neyret

Isabelle Bertrand

Aurelie Thuaire

Michael Stinco

Christophe Maleville

Marcel Broekaart

Xavier Baillin

Frédéric Allibert

Konstantin Bourdelle

Patrick Leduc

Muriel Martinez

Christelle Veytizou

Christophe Gourdel

Frédéric Metral

Luciana Capello

Khalid Radouane

Alexandre Chibko

Sothachett Van

Willy Michel

Zohra Chahra

Jean-Francois Gilbert

Sylvain Peru

Oleg Kononchuck

Aurélie Thuaire

Corentin Carmignani

Christophe Brun

Michael Lotissement Les Balcons Du Guiers Stinco

A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm&#xb7;cm and a thickness greater than 5 microns positioned on the first insulating layer.

Support for a semiconductor structure

Production of a device for connecting a nano-object to an external electrical system (SEE) including:

Device for connecting at least one nano-object associated with a chip enabling a connection to at least one external electrical system and method of fabrication thereof

Manufacturing of a device to connect at least one nano-object to an external electrical system, comprising a support provided with a semiconducting layer in which the first doped zones are formed at a spacing from each other, an external electrical system being connectable to the first doped zones, each first doped zone (8, 8) being in contact with a second doped zone on which a portion of the nano-object is located, the second doped zones being separated from each other and with a thickness less than the thickness of the first doped zones.

Device for connecting at least one nano-object and method of manufacturing it

An electronic device for measuring at least one electrical characteristic of an object, including a supporting base provided with at least two measuring units each including at least two sets of electrodes including electrodes, is provided. The electrodes of the sets of electrodes of the same measuring unit are interdigitated such that each electrode of one of the sets of electrodes of the measuring unit is spaced by an inter-electrode distance from an electrode, of the other of the sets of electrodes of the measuring unit, which is adjacent thereto, the electrodes differ in the features in respect of contact with the object and/or the electrode spacing thereof so as to make a differential current measurement.

Electronical device for measuring at least one electrical characteristic of an object

The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (Q) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.

Method of testing a semiconductor-on-insulator structure and application of said test to the fabrication of such a structure

A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950&#xb0; C. and less than 1200&#xb0; C.

Method for fabricating a structure

A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950&#xb0; C. for at least 10 minutes.

Method for manufacturing a semiconductor on insulator structure having low electrical losses

A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750&#xb0; C. and 850&#xb0; C. for a time period of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900&#xb0; C. and 1000&#xb0; C. for a time period of between 1 hour and 10 hour hours to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects.

Method for measuring defects in a silicon substrate by applying a heat treatment which consolidates and enlarges the defects

Method for manufacturing a semiconductor-on-insulator structure having low electrical losses

A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer. This method is noteworthy in that it includes conducting a thermal oxidation treatment of the initial substrate to cause oxidation of part of the silicon surface layer and form a thermal oxide thereon; conducting a first cycle of etching followed by cleaning of the silicon surface layer after the thermal oxidation treatment, wherein the etching of the first cycle is conducted so as to fully remove the thermal oxide from the silicon surface layer to thin it and lift off all unstable parts of the initial substrate at edges thereof to form a thinned substrate; conducting, after the first cycle, a second cycle of etching followed by cleaning of the silicon surface layer, wherein the etching of the second cycle is conducted to remove from the surface of the thinned substrate, polluting particles formed during the first etching cycle and that have deposited thereupon, in order to obtain a final SOI substrate having a thinned surface layer that forms an active layer for the substrate.

Method to thin a silicon-on-insulator substrate

Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure

The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Finishing method for a silicon on insulator substrate

The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.

Method for fabricating a compound-material wafer

The invention relates to a method for manufacturing compound material wafers, in particular, silicon on insulator type wafers, by providing an initial donor substrate, forming an insulating layer over the initial donor substrate, forming a predetermined splitting area in the initial donor substrate, attaching the initial donor substrate onto a handle substrate and detaching the donor substrate at the predetermined splitting area, thereby transferring a layer of the initial donor substrate onto the handle substrate to form a compound material wafer. In order to be able to reuse the donor substrate more often, the invention proposes to carry out the thermal treatment step to form the insulating layer at a temperature of less than 950&#xb0; C., in particular, less than 900&#xb0; C., and preferably at 850&#xb0; C. The invention also relates to a silicon on insulator type wafer manufactured according to the inventive method.

Method for manufacturing compound material wafers and corresponding compound material wafer

A method of planarization of a surface of a heteroepitaxial layer by chemical-mechanical polishing the disturbed surface of the heteroepitaxial layer with a polishing pad having a compressibility greater than 2% and less than 15% and a slurry comprising at least 20% of silica particles having an average diameter between about 70 and about 100 nm. This method allows to reach high polishing rates appropriated for eliminating surface defects on heteroepitaxial layers, such as crosshatch patterns, and to achieve, in the same time, a final polish that is desirable to facilitate further operations.

Planarization of a heteroepitaxial layer

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Murianette, France

Patrick Reynaud