Intel Corporation

Intle Corporation

Intel IP Corporation

Patrick R Morrow

Aaron D Lilak

Rishabh Mehandru

Kimin Jun

Willy Rachmady

Gilbert W Dewey

Anh Phan

Ehren Mannebach

Cheng-Ying Huang

Paul B Fischer

Hui Jae Yoo

Stephen M Cea

Mauro J Kobrinsky

Anand S Murthy

Donald W Nelson

Jack T Kavalieros

Robert S Chau

Shriram Ramanathan

Il-Seok Son

Tahir Ghani

Johanna M Swan

Adel A Elsherbini

Shawna M Liff

Brennen Karl Mueller

Ravi Pillarisetty

Van H Le

Abhishek A Sharma

Chia-Hong Jan

Sean T Ma

Richard E Schenker

Mark T Bohr

Qing Ma

Kevin O'Brien

Grant M Kloster

Cory E Weber

Paul A Packan

Ranjith Kumar

M Clair Webb

Marko Radosavljevic

Gerald S Pasdast

Sarah E Kim

Justin R Weber

Stephanie A Bojarski

Sansaptak W Dasgupta

Glenn A Glass

Valluri Ramana Rao

Prashant Majhi

Henning Braunisch

Kevin Lai Lin

Seiyon Kim

Christopher J Jezewski

Rajashree Raji Baskaran

Jun He

Anup Pancholi

Patrick H Keys

Michael Y Chan

Scott List

Uygar E Avci

Nicole K Thomas

Chandra S Mohapatra

Karthik Jambunathan

R Scott List

Kenneth C Cadien

Jihperng Leu

Tristan A Tronic

Urusa Alaan

Sridhar Balakrishnan

Thomas N Marieb

Colin T Carver

Chang-Min Park

Michael C Harmes

Sayed Hasan

Guanghai Xu

Kerryann M Foley

Satish Radhakrishnan

Sasikanth Manipatruni

Matthew V Metz

Ian A Young

Han Wui Then

Aleksandar Aleksov

Dmitri E Nikonov

Harold W Kennel

Yih Wang

Chuan Hu

Michael D Goodner

Bruce A Block

Nafees Kabir

Lawrence D Wong

Doug B Ingerly

Jeffery D Bielefeld

Jessica M Torres

Anurag Chaudhry

Andrew W Ott

Chi-Hwa Tsang

Daniel Pantuso

Tatyana N Andryushchenko

Sukru Yemenicioglu

Xiaorong Morrow

Alejandro X Levander

Don W Nelson

An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

Vertically spaced intra-level interconnect line metallization for integrated circuit devices

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying Mmetal layer and an underlying BMmetal layers to reduce capacitance.

SRAM with P-type access transistors and complementary field-effect transistor technology

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure

Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.

Asymmetric gate structures and contacts for stacked transistors

Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

Backside contact structures and fabrication for metal on both sides of devices

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Sideways vias in isolation areas to contact interior layers in stacked devices

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

Forming an oxide volume within a fin

Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.

Gate-all-around integrated circuit structures having removed substrate

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

Microelectronic assemblies

A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Stacked source-drain-gate connection and process for forming such

Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

Vertically stacked finFETs and shared gate patterning

An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

Wrap-around source/drain method of making contacts for backside metals

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Portland, OR, United States of America

Patrick R Morrow