International Business Machines Corporation

Patrick R Hansen

Wagdi William Abadeer

John P Connor

George Maria Braceras

Harold Pilo

R Dean Adams

Wayne Frederick Ellis

Robert Allen Groves

Phillip J Nigh

Robert Dean Adams

Jason Edward Rotella

Jonathan M McKenna

Edmond S Cooley

Steven Burns

Steven Leschuk

A ring oscillator (and test circuit incorporating the ring oscillator and test method therefor) includes an odd number of elements interconnected in a serially-connected infinite loop, each oscillator element having an associated programmable delay feature. The circuit can be used to measure effects of Negative Bias Temperature Instability (NBTI) in p-channel MOSFETs (PFETs).

System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)

An inductor is integrated in VLSI and ULSI technology products for very high frequency applications. The inductor is in a microstrip transmission line configuration which can be designed in a form of straight line, spiral line or Meander line. The inductor is formed by shorting the microstrip center conductor to the lower level ground plane at one end of the transmission line. This results in an inductance which, for a given design of transmission line, and in a specified frequency range, is independent of frequency, within the operating design range. The microstrip transmission line provides an inductance which could be used on any type of substrate, with either low or high resistivity. The microstrip transmission line could utilize two or all of the metal wiring levels of the technology, allowing a wide range of inductance and quality factor design tradeoffs. An important feature in this trade-off is the ability to utilize lower (below the inductor) metal wiring levels, as well as lower silicon and polysilicon areas for other than inductor design purposes, without affecting the operation of the inductor. This is because of the isolation properties of this inductor system. By utilizing isolation layers with low relative dielectric constant, Further enhancements of the system are achieved. The inductance of this system is constant within 10% over a frequency range extending from about 8 GHz to about 35 GHz This inductor system allows the design to be optimized, through several parameters, to achieve the desired performance.

Inductor for integrated circuits

A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Area efficient, sequential gray code to thermometer code decoder

An integrated circuit memory structure includes a main array of memory elements having wordlines and bitlines and a redundant array of redundant memory elements external to and connected to the main array. Each of the redundant memory elements can replace either one of the wordlines or one of the bitlines.

Redundant memory array having dual-use repair elements

Disclosed is a programmable impedance driver that includes two sets of impedance devices, two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage.

BIST circuit for variable impedance system

A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

Method and apparatus for programmable active termination of input/output devices

A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.

Structure and method of alternating precharge in dynamic SOI circuits

An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

Termination resistance independent system for impedance matching in high speed input-output chip interfacing

A testing device for slowly bleeding charge away from a primary node in a dynamic logic circuit. A properly functioning keeper device in the dynamic logic circuit will maintain the primary node in a precharged state even in the face of this bleeding device. If the logic circuit output flips after the bleeder device begins bleeding charge, a defective keeper device is thereby identified.

Testing method for dynamic logic keeper device

Termination impedance independent system for impedance matching in high speed input-output chip interfacing

A method and apparatus for detecting whether dynamic logic circuits are precharging properly. The method and apparatus uses a narrowed reset pulse to verify precharging is occurring as designed.

Method and apparatus for testing dynamic logic using an improved reset pulse

An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.

On-chip test circuit for evaluating an on-chip signal using an external

An impedance matching system and a network for automatic impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises a control circuit which varies a control voltage proportionally to the frequency of voltage transients that occur on the driver circuit output, an adjustment mechanism which provides a linear motion proportional to the control voltage, and an adjustable length transmission line whose length is adjusted in proportion to the frequency of voltage transients on the driver circuit output and whose impedance, which is purely reactive, is proportional to its length. The purpose of the adjustable length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver network to the driver circuit. In the preferred embodiment, the impedance matching network is manufactured on the same chip as the driver circuit.

On-chip automatic system for impedance matching in very high speed

A programmable variable impedance output driver circuit uses analog biases to match driver output impedance to load input impedance. A current mirror is used to obtain a measurement of an external resistance value for matching the impedance of a driven load. The mirrored current generates the voltage 'NBIAS' when passed through the resistively connected NFET. Similarly, the current is again mirrored and passed through a resistively connected PFET resulting in the voltage 'PBIAS'. The analog bias voltages, NBIAS and PBIAS are used to vary the impedance of complementary FETs in an impedance matched driver for a high degree of dI/dt control. The driver provides a high degree of flexibility because its turn-on and turn-off characteristics do not depend on a combination of digital control signals connected directly to the driving FETs as in the prior art. Instead, the PBIAS and NBIAS signals provide analog controls which may be applied to single transistors whose impedance changes as PBIAS and NBIAS increase or decrease.

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Essex Junction, VT, United States of America

Patrick R Hansen