Apple Inc.

Patrick R Cruce

Hyunwoo Nho

Jie Won Ryu

Sun-il Chang

Wei Xiong

Hyunsoo Kim

Wei Hsin Yao

Kingsuk Brahma

Mahesh B Chappalli

Hao-Lin Chiu

Kwang Soon Park

Yao Shi

Ionut A Mirel

Ruicong Chen

Nicolas Le Dortz

Embodiments herein provide various apparatuses and techniques to efficiently mitigate front-of-screen (FoS) artifacts that may occur due to voltage fluctuations due to alternating current (AC) or direct current (DC) mechanisms that may occur in a variety of pixel types. In one embodiment, emission profile awareness circuitry may be implemented to mitigate for FoS artifacts due to DC mechanisms. Two-dimensional (2D) digital compensation circuitry may address the DC portion of the voltage fluctuations by accounting for an emission profile applied to content displayed on an electronic display. In some embodiments, the 2D digital compensation circuitry may compensate for the AC portion of the voltage fluctuations by duplicating the AC voltage fluctuations via voltage error subtraction circuitry and voltage error accumulation circuitry.

Feedforward compensation of high-luminance banding Mura compensation

An electronic device may include an electronic display having a gate-on-array (GOA) that generates gate signals in response to an activation signal, pixels that activate in response to a combination of the gate signals and data signals indicative of image data, and sensing circuitry. The sensing circuitry may measure a characteristic response of a gate signal a characteristic response of one or more pixels, or both and compare the characteristic responses to baselines. The electronic device may also include compensation circuitry that applies a compensation to the activation signal and/or to the image data based on the comparisons between the characteristic responses and the baselines.

Display panel transistor gate-signal compensation systems and methods

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Campbell, CA, United States of America

Patrick R Cruce