Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Globalfoundries Inc.

Ferroelectric Memory Gmbh

Globalfoundries Dresden Module One Limited Liability Company & Co. Kg.

Globalfoundaries Inc.

Patrick Polakowski

Konrad Seidel

Johannes Mueller

Dina Triyoso

Thomas Kaempfe

Maximilian Ludwig Drescher

Stefan Riedel

Sanford Chu

Stefan Müller

Robert Binder

Joachim Metzger

Tarek Ali

Mark Gerard Nolan

Wenke Weinreich

According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Memory cell, capacitive memory structure, and methods thereof

The present invention relates to an integrated electronic circuit and method of making comprising a first transistor () and a ferroelectric capacitor (). The ferroelectric capacitor () comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor ().

Integrated electronic circuit and method of making comprising a first transistor and a ferroelectric capacitor

According to various aspects, a method of forming one or more remanent-polarizable capacitive structures, the method including forming one or more capacitive structures, each of the one or more capacitive structures includes: one or more electrodes, one or more precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range from about 1 nm to 100 nm and a second dimension in a range from about 1 nm to about 30 nm; and, subsequently, forming one or more remanent-polarizable structures comprising a crystalline remanent-polarizable material based on a crystallization of a precursor material of the one or more precursor structures.

Remanent polarizable capacitive structure, memory cell, and methods thereof

The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor.

Ferroelectric based transistors

The present invention relates to a voltage-controllable capacitor comprising a first electrode layer () composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (), a ferroelectric interlayer () having a thickness that is less than the thickness of the first electrode layer (), and a second electrode layer () composed of a non-ferroelectric material. The ferroelectric interlayer () is arranged between the first electrode layer () and the second electrode layer ().

Voltage-controllable capacitor comprising a ferroelectric layer and method for producing the voltage-controllable capacitor comprising a ferroelectric layer

The present invention relates to an integrated electronic circuit comprising a first transistor () and a ferroelectric capacitor (). The ferroelectric capacitor () comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor ().

Integrated electronic circuit comprising a first transistor and a ferroelectric capacitor

The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Complex circuit element and capacitor utilizing CMOS compatible antiferroelectric high-k materials

The present disclosure provides a semiconductor device comprising a substrate, an undoped HfOlayer formed over the substrate and a TiN layer formed on the HfOlayer. Herein, the undoped HfOlayer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfOlayer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfOlayer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfOlayer.

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Dresden, Germany

Patrick Polakowski