Texas Instruments Corporation

Patrick Peter Siniscalchi

William Robert Krenik

Richard K Hester

Davy H Choi

David John Baldwin

Mayank Garg

Bryan E Bloodworth

Eric Christian Blackall

Roy Clifton Jones, Iii

Weibiao Zhang

Donald Cook Richardson

Alexander Noam Teutsch

Glenn H Westphal

Narasimhan Trichy Rajagopal

Michael D Aragon

Geert A De Veirman

Sen-Jung Wei

Disclosed examples include amplifier circuits with a first stage to amplify an input voltage signal according to a first stage gain to provide a first stage output voltage signal, and a second stage to provide an amplifier output voltage signal. A bias circuit provides an amplifier bias current signal to a current mirror circuit coupled with the first stage to control a first stage bias current, and an adjustment circuit to reduce the amplifier bias current signal and increase the first stage gain when the input voltage signal is near a first supply voltage or a second supply voltage.

Amplifier circuit and method for adaptive amplifier biasing

A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.

Class DH amplifier

Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include one or more discrete components in series with the load, but this degrades performance. Here, however, circuit is provided (which includes sample-and-hold circuit) that accurately measures load currents without inhibiting performance and that is not inhibited by the phase differences between the load voltage and load current.

Method and apparatus for sensing a current for varying impedance loads

A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Variable timing switching system and method

Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Switching system with reduced EMI

Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

Process, supply, and temperature insensitive integrated time reference circuit

A system and method for driving a load at a desired operating level. A driver is connected to a load. The load can be selected from a plurality of loads by a selection system, such as a multiplexer, or a single load can be utilized. Feedback from the load is provided to the driver for achieving the desired operating level. A zero temperature coefficient resistance formed by two resistors having different resistances can be used so that the driver emulates an ideal resistor having a substantially zero temperature coefficient, providing a temperature independent current to the load.

System and method for driving one or more loads

A circuit topology for gain boosted high-swing folded cascode has been improved to maximize the available dynamic range in applications having low supply voltage requirements. The circuit includes an improved gain boost amplifier that maximizes the available dynamic range for applications having low supply voltage requirements. The improved gain boosting amplifier includes a differential pair of input transistors connected to a current mirror, wherein a pair of current sources supply current to each lead of the current mirror. One lead of the current mirror is level-shifted by a transistor coupled to another current source, wherein the coupling of the transistor and the current source form the output of the amplifier. Effectively, the amplifier consists of a level shifter and a series common-drain, common-gate amplifier. A reduction in transconductance gfrom the series combination is compensated by a current mirror ratio (K:1) between the level shift and the common-drain, common-gate amplifier.

High-swing folded cascode having a novel gain-boost amplifier

A control voltage window generator that tracks process, voltage supply, and temperature variations for a voltage controlled oscillator includes: a first transistor of a first conductivity type coupled between a supply voltage node and an upper control voltage node; and a second transistor of a second conductivity type coupled to the upper control voltage node to compensate for process variations in devices of the first conductivity type. Additionally, a target pull-in voltage generator includes circuitry for providing a pull-in control voltage that will always be inside the control voltage window, and also tracks process, voltage supply, and temperature variations.

Process tracking limiter for VCO control voltages

A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable by controlling a current applied thereto. A first current source provides a first control current controllable by controlling a voltage applied thereto that has a predetermined range. A first current mirror is adapted to mirror the control current to the current controlled oscillator. A second current source is adapted to provide a second control current for mirroring to the current controlled oscillator by the first current mirror when the control voltage is in a low portion of the range.

Gain control circuits for voltage controlled oscillators

A voltage controlled oscillator () includes a voltage to current portion () that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain response. To compensate for low-frequency variations, a portion of the control current (I), non-compensated control current I(), is subtracted from a reference current I() and the result, a low-frequency compensating control current, I(), is added to the non-compensated control current I(). To compensate for high frequency variations, a number of differential transistor pairs () are provided that have tail currents that are inversely proportional to the processing. One input () to all the differential pairs is connected to the VCO's control voltage while the other inputs () are connected to successively increasing voltages in the control voltage range. One output, I(), of all the differential pairs is summed with the non-compensated control current I() while the other output of each differential pair is connected to the power supply. By adjusting the amount of non-compensated control current I() provided to transistor Musing the low frequency gain compensation circuitand high frequency gain compensation circuit, VCO () provides for a process-insensitive, substantially constant gain VCO.

Voltage controlled oscillator having control current compensation

A segmented current mode DAC () is disclosed herein having a current matching circuit () that compensates for the current mismatch produced by the transistors of each current source. This segmented current mode DAC () includes an input stage (), a first and second controllable current source (), a current matching circuit (), and an output switching network (). The first controllable current source () couples to receive a mirrored current as provided by the input stage () to provide a current source output controllable in current increments responsive to the M least significant bits for converting of the digital signal to analog form, where M is less than N. The second controllable current source () couples to receive the mirrored current to provide a current source output controllable in current increments responsive to the N&#x2212;M most significant bits for converting of the digital signal to analog form. The current matching circuit () couple between the first and second controllable current sources () to match the current of the first controllable current source () and the second controllable current source (). Specifically, the current matching circuit () connects between each sub-DAC () to force the drain-to-source voltage of a transistor () representing the first bit of the MSB binary weighted sub-DAC () to be the same as the drain-to-source voltage of the transistor () representing the LSB thermometer decoded sub-DAC ().

Segmented, current-mode digital-to-analog converter

The asymmetric digital subscriber line receive channel includes: first and second external resistorsandcoupled to a telephone lineand; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistorsand; and a fine programmable gain amplifier PGAcoupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistorsandand the coarse programmable gain amplifier CPGA.

ADSL front-end in a low voltage process that accommodates large line voltages

A process-insensitive, highly-linear, constant transconductance circuit employs a CMOS multiplier in the signal path that is offset biased with a specific combination of currents to compensate for variations in transconductance due to resistor processing variations.

Process-insensitive, highly-linear constant transconductance circuit

A hard disk drive system (10) includes a read/write head (21) for reading and writing data to and from a rotating magnetic disk (12). The read/write head includes a portion which is a magneto-resistive read head (36), the output of which is supplied through a preamplifier (26) to a read channel circuit (27). The read head has a nonlinear transfer function. The read channel circuit includes an asymmetry compensation circuit (62), which generates an analog compensation signal by squaring an output signal from the read head and scaling by an asymmetry factor (.alpha.'). The analog compensation signal is combined with the analog output signal in order to obtain a corrected analog signal, which is substantially free of the distortion introduced by the read head.

Growing community of inventors

Sachse, TX, United States of America

Patrick Peter Siniscalchi