National Semiconductor Corporation

Patrick P Fasang

Walter Francis Bridgewater, Jr

Daryl E Mullins

In a built-in self test ('BIST') circuit for on-chip testing of an integrated circuit memory, a control logic circuit is responsive to an external signal on a test select pin for controlling the BIST operations of the major circuit groups thereof. The major circuit groups include an address PRPG (pseudo-random pattern generator), which selectively furnishes test addresses or mission addresses to the memory; a data PRPG, which selectively furnishes test data or mission data to the memory; a PSA (parallel signature analyzer) PRPG, which furnishes mission data from the memory in normal mode and determines a signature in test mode; and a decoder, which compares the signature determined by the PSA PRPG with a known correct signature and sets a flag to indicate memory pass/fail. The BIST circuit is modular and extendable for any N-word by M-bit memory. To this end, a counter in the control logic circuit comprises a plurality of counter slices, the address PRPG comprises a plurality of address slices, the data PRPG comprises a plurality of data slices, and the PSA PRPG comprises a plurality of PSA slices. The BIST circuit is formed by replicating slices for the major circuit groups. Only certain feedback paths in the major circuit groups and certain control signal combinatorial circuits in the control logic require customization.

Built-in self test for integrated circuit memory

An architecture and device for testing mixed analog and digital VLSI circuits, wherein the digital circuit portions of the chip are grouped into a digital block, and the analog circuit protions of the chip are= grouped into an analog block. Analog signals are provided to the digital block through an A/D transducer, and digital signals are provided to the analog block through a D/A transducer. The analog and digital blocks may be isolated from each other by a digital input multiplexer disposed between the A/D transducer and the digital block, and by an analog input multiplexer disposed between the D/A transducer and the analog block. To minimize the number of pins required to implement the architecture, multiplexers are connected to accessed circuit nodes in the analog block and the digital block for selectively communicating signals from the accessed nodes to external output pins.

Growing community of inventors

Saratoga, CA, United States of America

Patrick P Fasang