General Dynamics Corp., Pomona Division

Hughes Missile Systems Company

Patrick O Nunally

A neural processor element for use in a neural network includes a synaptic base weighting circuit which responds to an excitory input in the form of a stream of pulses of a first polarity which represents a sum of synaptic weights and an inhibitory input in the form of a stream of pulses of a second polarity which represents a sum of synaptic weights. The synaptic weight of the neural processor element is generated by summing the excitory and inhibitory pulse streams to produce a signal of varying level magnitude. This signal is subjected to a thresholding function which generates a pulse having a width corresponding to the sum of excitory and inhibitory pulse streams, this pulse width representing the synaptic weight for the neural processor element.

Neural processor element

A frequency-based neural network in which the state of a neuron is indicated by the frequency of an impulse stream emitted by the neuron uses an interconnectivity structure employing a frequency-modulation multiplexing scheme to weight and communicate the pulse stream from an emitting neuron to receiving neurons in another network level.

Neural network architecture

Integration at the chip level is supported by an architecture for self-testing and self-configuration of an integrated circuit. Self-testing requires the generation of test signals based on primary root polynomials, application of the test signals to functionally redundant modules, and evaluation of the response of the modules to the test signals. The response produced by a module is compared against the response predicted from error-free operation of the module. Modules whose responses correspond to the expected responses are interconnected for circuit operation. All of the architecture for self-testing and self-configuration is integrated with the tested and configured modules.

Self-testing and self-configuration in an integrated circuit

A fault-resistant, solid-state line driver having a pair of P-type transistors in series between a bus output and a voltage source, a pair of N-type transistors in series between the bus output and a connection to ground, and a pair of input lines, one of the input lines being connected to both the gate of the P-type transistor closest to the voltage source and the gate of the N-type transistor closest to the bus output, the other input line being connected to both the gate of the P-type transistor closest to the bus output and the gate of the N-type transistor closest to the connection to ground. Such a line driver is particularly useful in devices utilizing wafer-scale levels of integration, as the failure of any one of the driver's transistors will not result in a shorting of the bus output to either ground or the voltage source.

Fault-resistant solid-state line driver

A system and process, including a combination of a solder well and a vacuum system wherein micro through holes are filled with solder. A PC board or the like is supported for contact with solder on one side and with a vacuum apparatus for the application of a vacuum to the other side so that solder is drawn into the through holes for establishing electrically conductive connections therethrough.

Growing community of inventors

Diamond Bar, CA, United States of America

Patrick O Nunally