Advanced Micro Devices Corporation

Fujitsu Corporation

Globalfoundries Inc.

Patrick N Conway

Kazunori Masuyama

Sudheer Miryala

Jeremy J Farrell

Takeshi Shimizu

Vydhyanathan Kalyanasundharam

William Alexander Hughes

Hitoshi Oi

Kevin Michael Lepak

Toshio Ogawa

Frederick Daniel Weber

Benjamin Tsien

Sergey Blagodurov

Jeffrey Roy Dwork

Yukihiro Nakagawa

Eric Christopher Morton

Greggory D Donley

Elizabeth Morrow Cooper

Michael K Fertig

Martin Sodos

Yasushi Umezawa

Stanley Ames Lackey, Jr

Yukio Nishimura

John David McCalpin

Norio Kaido

Prabhu Murthy

Jung Rung Jiang

Timothy E Landreth

Cissy Xumin Yuan

A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.

Redirecting data to improve page locality in a scalable data fabric

A communication bypass mechanism accelerates cache-to-cache data transfers for communication traffic between caching agents that have separate last-level caches. A method includes bypassing a last-level cache of a first caching agent in response to a cache line having a modified state being evicted from a penultimate-level cache of the first caching agent and a communication attribute of a shadow tag entry associated with the cache line being set. The communication attribute indicates prior communication of the cache line with a second caching agent having a second last-level cache.

Acceleration of cache-to-cache data transfers for producer-consumer communication

A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. A method includes profiling a stream of memory accesses to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in the stream of memory accesses. The method includes periodically migrating to a region migration cache contents of a region of main memory selected based on the access frequency ranked list. The method includes storing a memory address range corresponding to the contents of the region migration cache in a tag map.

Region migration cache

A probe filter determines whether to issue a probe to at least one other processing node in response to a memory access request, and includes a region probe filter directory, a line probe filter directory, and a controller. The region probe filter directory identifies regions of memory for which at least one cache line may be cached in a data processing system and a state of each region, wherein a size of each region corresponds to a plurality of cache lines. The line probe filter directory identifies cache lines cached in the data processing system and a state of each cache line. The controller accesses at least one of the region probe filter directory and the line probe filter directory in response to a memory access request to determine whether to issue the probe, and does not issue any probe in response to a read-only request.

Region probe filter for distributed memory system

A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.

Coherency probe with link or domain indicator

A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

Method and apparatus for selectively bypassing a cache for trace collection in a processor

A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.

Method and apparatus for reducing processor cache pollution caused by aggressive prefetching

A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of a shared cache memory subsystem, such as an L3 cache. Directory entries are stored within the shared cache memory subsystem to provide indications of lines (or blocks) that may be cached in exclusive-modified, owned, shared, shared-one, or invalid coherency states. The absence of a directory entry for a particular line may imply that the line is not cached anywhere in a computing system.

Snoop filtering mechanism

In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.

Push for sharing instruction

A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.

Speculative memory prefetch

In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.

Communicating between partitions in a statically partitioned multiprocessing system

A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node and initiating a first load operation to said cache data block from a second processing node subsequent to initiating said first store operation; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation. The method may further include initiating a second store operation to said cache data block from said second processing node subsequent to initiating said first load operation; and assigning a migratory directory state to said coherence directory entry in response to initiating said second store operation, where the migratory directory state is distinct from a modified directory state.

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer

A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node; assigning a modified cache state to said cache data block in response to initiating said first store operation. The method may further include initiating a first load operation to said cache data block from a second processing node; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation, where the pairwise-shared directory state is distinct from a shared directory state.

A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, and a private page indication that indicates whether any other processors have an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page. The processor also includes a memory controller that may inhibit issuance of a probe message to other processors in response to receiving a write memory request to a given memory page. The write request includes a private page attribute that is associated with the private page indication, and indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page.

Method and apparatus for detecting and tracking private pages in a shared memory multiprocessor

A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node including the first cache and assigning a modified cache state to the cache data block in response to initiating the first store operation. The method may further include evicting the cache data block from the first cache subsequent to initiating the first store operation, storing the cache data block in a remote cache in response to the evicting, and assigning a remote directory state to a coherence directory entry corresponding to the cache data block in response to storing the cache data block in the remote cache, where the remote directory state is distinct from an invalid directory state.

Growing community of inventors

Sunnyvale, CA, United States of America

Patrick N Conway