Texas Instruments Corporation

Patrick Michael Teterud

Benjamin Lee Amey

Sigfredo Emanuel Gonzalez Diaz

Hung Nguyen

Kenneth James Maggio

Thomas Cougar Van Eaton

Indumini W Ranmuthu

Sombuddha Chakraborty

Shanmuganand Chellamuthu

Echere Iroaga

Ashish Manjrekar

Dingkun Du

Seenu Gopalraju

Theodore Ernest Yu

Ali Motamedi

Keith Thomas Sanders, Jr

Donghwi Kim

Jiangfeng Wu

A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

High-side gate over-voltage stress testing

A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.

In described examples, a switching mode power supply includes an output filter, a driver, a pulse width modulator, and pulse adaptation circuitry. The output filter is configured to provide output of the switching mode power supply. The driver is coupled to the output filter and is configured to switch current to the output filter. The pulse width modulator is configured to generate pulses that control switching of current by the driver. The pulse width modulator includes spread spectrum logic configured to randomize timing of the pulses generated by the pulse width modulator. The pulse adaptation circuitry is configured to identify an instantaneous excursion of the output of the switching mode power supply beyond a predetermined threshold, and to modify the randomized timing of the pulses produced by the pulse width modulator based on the identified instantaneous excursion.

Switching mode power supply with adaptively randomized spread spectrum

A circuit includes a comparator that monitors a transient with respect to a predetermined threshold at the output of a voltage regulator and generates a compensation signal if the transient exceeds the predetermined threshold. A dynamic current pull-down block is triggered from the compensation signal of the comparator and operative with an output stage of the voltage regulator to mitigate the transient at the output of the voltage regulator by concurrently activating a plurality of current pull-down switches during the transient and sequentially deactivating each current pull-down switch of the plurality of current pull-down switches after its predetermined deactivation delay for each current pull-down switch.

Dynamic current pull-down for voltage regulator

In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.

Method and circuitry for regulating a voltage

An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information; the apparatus includes: (a) a read signal control unit receiving the input signal at a control unit input locus; the control unit is coupled with the output locus and controls the read signal; (b) a plurality of switches; and (c) a plurality of bias arrays coupled with the switches. A first bias array set cooperates with the plurality of switches in a first orientation to couple the first bias array set with the control unit to establish a first operational mode. A second bias array set cooperates with the plurality of switches in a second orientation to couple the second bias array set with the control unit to establish a second operational mode.

Apparatus and method for providing a read signal for an information processing device

A system and method are disclosed to help protect a node of associated circuitry from overshooting or undershooting, such as can be associated with power up or other transitional modes. The protection is implemented by diode connecting a transistor, which has its base electrically coupled to the node during the transitional mode. Either after a predetermined time period or after the voltage at the node has reached a desired level, the diode connection can be removed to permit normal operation to begin in which a bias can be provided to the node.

System and method for implementing soft power up

An ultra-fast drive circuit ( ) providing a rail-to-rail drive voltage at an output node (N ). A pair of bipolar output transistors (Q , Q ) are selectively driven via a FET drive circuit ( ), and by a control circuit ( ) to achieve a rail-to-rail output voltage (V &minus;V ) that is very fast. The drive FETs comprise three serially connected FETs (M , M , M ) whereby the middle FET (M ) is the control FET effecting the control of the output transistors (Q , Q ). The other two FETs (M , M ) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N ), depending on the state of the middle FET (M ). The control FETs ( ) provide two output control signals ( ) to the output transistors (Q , Q ), with the control line ( ) controlling the state of the middle switching FET (M ).

Ultra-fast voltage drive

An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and ringing while allowing for higher data rates. The discharge circuit is turned on after the head voltage or current reaches an overshoot condition. In preferred embodiments, the discharge circuit includes variable discharge capability by selecting one or more parallel drive transistors or varying a variable delay in the discharge circuit or any combination of both variables. Both can be controlled by a word written to the disk drive pre-amp over the serial control port.

Overshoot control for a hard disk drive write head

A HDD write driver circuit ( ) having two sets of boost devices (Q , M , and Q , M ) which are temporarily turned on during a current reversal to boost the normal current and increase the differential transient voltage across the coil (LS) while decreasing the TRTF. During a current reversal cycle, one set of transistors is turned on while the other set is left off. The on set to pulls the node at one end of the coil substantially to the positive rail, and pulls the other node at the other end of the coil substantially to the lower rail (V ). The boost FETs (M , M ) are preferably large PMOS devices that must be driven hard to achieve a quick transient switching time. Advantageously, when one of the PMOS FETs (M , M ) are on, the associated series resistor (RS) is bypassed. The voltage at nodes HX and HY are no longer limited by an IR voltage drop associated with a resister (RS) therefore increasing the differential transient voltage across nodes HX and HY by increasing the maximum transient voltage of the pull-up node. Preferably, each node (HX, HY) of the coil (LS) can be pulled to within 0.2 volts of the positive rail.

Enhanced voltage drive circuit for HDD write driver

An improved write drive circuit which provides an adjustable writer drive current and overshoot transient for a H-bridge drive circuit in a hard disk drive. The invention uses a variable capacitor circuit to give an initial boost to the write driver transistors. In a preferred embodiment, the capacitance of the variable capacitor is controlled by a word written to the disk drive pre-amp over the serial control port.

Adjustable writer overshoot for a hard disk drive write head

A clamp circuit for clamping a terminal of an H-bridge circuit. The clamp circuit is capable of being applied to a voltage in excess of 5V including 8 volts.

8V ring clamp circuit

An active damping circuit damps the ringing effect caused by a write circuit for a disk drive. The circuit includes upper switches and lower switched current sources. A capacitive feedback is connected between the output and the lower switched current sources.

Active damping circuit

An improved write drive circuit which reduces the ringing and overshoot transients of an H-bridge drive circuit for a hard disk drive. The invention uses a damp circuit which minimizes the amount of capacitance on the outputs of the write driver while still accomplishing the dampening of the transient ring. In a preferred embodiment, the damp circuit is a ring clamp circuit which includes a resistor connected to each node of the write head. Each resistor is then connected to the emitter of a npn transistor where the transistors have a commonly enabled gate and a common collector connected to a source voltage.

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Plano, TX, United States of America

Patrick Michael Teterud