Analog Devices,inc.

Patrick Michael Mitchell

Timothy J Cummins

Eamonn J Byrne

Dara Joseph Brannick

Brian John O'Mara

An emulator couplable to an integrated circuit, the integrated circuit including a micro controller, a DMA controller, memory means and an ADC and the emulator being operable to read a block of data stored in a plurality of memory locations of the memory means and graphically to display a representation of at least a portion of the block of data. An integrated circuit including an ADC and reprogrammable non-volatile memory means, the ADC being arranged to read calibration values from the non-volatile memory means. An integrated circuit including a microcontroller, a DAC selected from a group consisting of a string DAC and a current source DAC and an operational amplifier coupled to the DAC output. An integrated circuit includes analog and digital circuitry, and has only two polysilicon layers on a C-MOS substrate.

Integrated circuit with a high resolution analog to digital convertor, a microcontroller and high density memory and an emulator for an integrated circuit

An integrated circuit including a DMA controller, an ADC having a plurality of conversion channels and address and data ports for connection to external memory means, the DMA controller being arranged to read a channel id from the memory means using the address and data port which channel id is representative of one of the said conversion channels, to pass the read channel id to the ADC, to cause the ADC to perform an analog-to-digital-conversion on the conversion channel represented by the channel id, to receive the conversion result from the ADC and to write the conversion result back to the memory means using the address and data ports. Also, an integrated circuit including a microcontroller having an output port, an address valid output line, a latch coupled to the output port, and a latch control fine coupled to the latch control of the latch the microcontroller being operable to present a first range of address bits at its output port, to activate the latch control line to cause the latch to latch the first range of bits, to present a second range of address bits at its output port and to activate the address valid line to indicate that the combination of the first and second ranges present on the latch outputs and the output port respectively, are valid.

Analog-to-digital converter that preseeds memory with channel identifier data and makes conversions at fixed rate with direct memory access

A data processor is provided with an embedded debugger. The debugging function is provided by the execution of a debugging program which is stored in reserved, non-volatile memory which is internal to the data processor. During the debug mode, the data processor allows the internal registers used during execution of a user program to be examined. Debug operation can be initiated via debug instruction which replaces an existing instruction in the user code, the replaced instruction being held in a special purpose register such that it can be executed on return from the debug mode. Single step operation of the data processor can be performed in debug mode and data and instructions can be exchanged with the data processor in debug mode, optionally via a single pin so as not to sacrifice any user resources.

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Killaloe, Ireland

Patrick Michael Mitchell