Aehr Test Systems, Inc.

Aeha Test Systems

Patrick M Shepherd

James F Tomic

Jovan Jovanovic

Donald Paul Richmond, Ii

Scott E Lindsey

Mark Charles Carbone

Kenneth W Deboe

Frank Otto Uher

Thomas T Maenner

Long V Vu

Paul W Burke

Jeffrey L Tyson

Doan D Cao

Jeffrey A Brehm

John Dinh Hoang

William D Barraclough

Mikhail A Alperin

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Apparatus for testing electronic devices

A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

Method and system for testing memory programming devices

A high density interconnect system (30) employs contact fingers (32) on both surfaces (34) and (36) of burn-in PCB (38), feed-through PCB (40) and driver PCB (42). Each of the PCBs (38), (40) and (42) has a card-edge connector (44), (46) and (48). The feed-through PCB (40) has a second card-edge connector (40) and a second set of contact fingers (32), since it mates with both the burn-in PCB (38) and the driver PCB (42). The contact fingers (32) and the card-edge connectors (44), (46), (48) and (50) of each PCB (38), (40) and (42) mate inversely with each other on adjacent PCBs, i.e., the card-edge connector (44) of the burn-in PCB (38) mates with the contact fingers (32) of the feed-through PCB (40), and the card-edge connector (46) of the feed-through PCB (40) mates with the contact fingers (32) of the burn-in PCB (38), for example. The same relationship exists between the card-edge connector (50) of the feed-through PCB (40), the card-edge connector (48) of the driver PCB (42) and the contact fingers (32) of the feed-through PCB(40) and the driver PCB (42).

High-density interconnect technique

Growing community of inventors

San Jose, CA, United States of America

Patrick M Shepherd