International Business Machines Corporation

Intel Corporation

Other

Patrick M Bland

Richard Gerard Hofmann

Mark Edward Dean

Ralph M Begun

Dennis L Moeller

Lance M Venarchick

Richard Bealkowski

Nader Amini

Bechara F Boury

Jimmy Grant Foster, Sr

Robert T Jackson

Daniel R Cronin, Iii

Jayesh M Joshi

James P Kardach

Robert Brett Tremaine

Terence J Lohman

Thomas Basil Smith, Iii

Michael Edward Wazlowski

Philip E Milling

Suksoon Yong

Sagi Katz

Daryl Carvis Cromer

Makoto Ono

Moises Cases

Vinod Kamath

William Joseph Piazza

Richard Edwin Harper

Justin Potok Bandholz

Dhruv Manmohandas Desai

Alfredo Aldereguia

Gene J Gaudenzi

Yiyu L Chen

Stephen Douglas Weitzel

Ivan R Zapata

Ryuji Orita

Marcus Alan Baker

Brian David Allison

Kevin G Kramer

Andrew S Heinzmann

William Alan Wall

Angela Beth Dalton

Susumu Arai

Susan L Tempest

Grant L Clarke, Jr

Amy Louise Kulik

Kit H Wong

Amitayu Das

Randoph S Kolvick

Rodger M Stutes

Jefferey B Williams

William H Bolt

Brandon R Wyatt

Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.

Memory access to a dual in-line memory module form factor flash memory

Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.

Airflow barriers for efficient cooling of memory modules

Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules ('DIMMs') and each DIMM capable of on-die termination ('ODT'). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (&#x2018;POST&#x2019;) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.

Memory downsizing in a computer memory subsystem

An improved method is provided for managing workload on a multi-server computer system. In one embodiment, a subset of servers is selected according to an anticipated net workload. The remaining servers in the system may be powered off to conserve energy and prolong equipment life. Workload is dynamically apportioned among the subset of servers at selected intervals to more uniformly distribute the mean and variance of the workload among the subset of servers. More particularly, the mean and the variance for each of a plurality of workload units are equally weighed in determining a ranking of the workload units. The workload units may be ordered according to a mathematical combination of the mean and variance, such as the sum or product of mean and variance for each workload unit. The workload units are allocated among the subset of servers in according to rank, such as by assigning the workload units to the servers in a reverse round-robin fashion according to rank. Predictive power management schemes such as DVS and DVFS may then be used to control power to the servers.

Workload apportionment according to mean and variance

Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Directing interrupts to currently idle processors

Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.

Providing independent clock failover for scalable blade servers

A method and apparatus are disclosed for detecting a presence of a device. Specifically, a method and a system are disclosed that may comprise providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, identifying the absence of the device if no presence detection signal is received through the pair of differential clock signal lines, identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines, and notifying a system management module of the presence of the device.

Method and apparatus for detecting a presence of a device

An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant 'duplex' computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.

Low cost and high RAS mirrored memory

Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.

Methods and arrangements to enhance a bus

An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant &ldquo;duplex&rdquo; computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.

A computer system with a shared-buffer memory includes a plurality of interconnected host systems. Each of the host systems includes system random access memory, with a portion of the system random access memory defined as shared-buffer memory. A system memory controller determines if the host has updated the shared-buffer memory, and if so, signals that the shared-buffer memory has been updated. This signal is accomplished by initiating a PCI Special Cycle which indicates the location and length in the shared-buffer of the update. A buffer control and interconnect device receives the signal from the system memory controller that the shared-buffer memory has been updated, reads the update from the shared-buffer memory, and exports the update. The exported update is received at the buffer control and interconnect device of each of the other host systems. The receiving buffer control and interconnect device writes the update to its shared-buffer memory.

Computer system and method for maintaining an integrated shared buffer memory in a group of interconnected hosts

A system and method for providing network communications between personal computer systems using USB communications. The disclosed USB networking hub allows multiple hosts to exist in a USB-based network. The networking hub includes an integrated virtual network adapter, which provides for communications among and between multiple hosts.

USB-based networking and I/O hub

A system for partitioning and allocating individual PCI slots within a Primary Host Bridge (PHB) in a partitioned computer system is provided. An innovative PHB system is included which allows a PCI slot to be dynamically assigned to one or more partitions at a given time, allowing for more efficient allocation of system resources.

PCI slot control apparatus with dynamic configuration for partitioned systems

A method and system for hot-plugging a processor subsystem to a system bus of a data processing system while said data processing system is active, where the system bus comprises multiple positions for supporting hot-pluggable processor subsystems, where each processor subsystem includes a processor and associated voltage regulator module. Power is applied to a processor subsystem in response to an indication that the processor subsystem has been added to the system bus of the data processing system. Initialization routines are performed on the processor within the processor subsystem through a controller which transmits initialization data to the processor independent of the system bus, such that additional processor subsystems are integrated into the data processing system with minimal effect on any existing processors operating on the system bus.

Method and system for hot-plugging a processor into a data processing system

A method and arrangement is provided to support both fast Programmed Input/Output (PIO) and third party Direct Memory Access (DMA) data transfers between a system memory and Integrated Drive Electronics (IDE) drives. A DMA controller attached to an ISA bus supplies address, read and write signals in third party DMA data transfers. An IDE controller provides control signals to support the DMA data transfers. The IDE controller additionally provides address and control signals to support the PIO data transfers at local bus speeds. A local bus-ISA bridge is incorporated to support the system memory that resides on the local bus. An arbitration circuit arbitrates access to the ISA bus, and allows the IDE controller to seize the ISA bus for fast PIO data transfer.

Local bus-ISA bridge for supporting PIO and third party DMA data

Growing community of inventors

Delray Beach, FL, United States of America

Patrick M Bland