Xilinx, Inc.

Patrick Lysaght

Graham F Schelle

Paul R Schumacher

Yi-Hua Edward Yang

Parimal Patel

Adam P Donlin

Brandon Blodget

Yun Qu

Paul M Hartke

Peter K Ogden

Bernard J New

Austin H Lesea

Philip Bryn James-Roxby

Tim Tuan

Delon Levi

Goran Hk Bilski

Alan M Frost

Hayden Kwok-Hay So

Anthony Brandon

Yi-Hua E Yang

Rebuilding a next compile-time Intellectual Property (IP) core can include determining an IP core included in a runtime design for an integrated circuit (IC) by evaluating metadata of the runtime design. The IP core specifies a circuit configured for implementation in programmable circuitry of the IC. Source code for the IP core may be retrieved automatically based on source data read from the metadata. A new instance of the IP core, including the source code, may be generated in a memory. The new instance of the IP core may be included within a new compile time design.

Runtime intellectual property core metadata to rebuild a next-compile-time intellectual property core

An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay and a processor coupled to the programmable circuitry. The processor can be configured to control the programmable circuitry through execution of a framework. The framework provides high-productivity language control of implementation of the overlay in the programmable circuitry.

Productivity platform using system-on-chip with programmable circuitry

A computer-implemented design flow can include, within a circuit design for an integrated circuit, determining a portion of the circuit design that is a candidate for implementation as a runtime customizable circuit and determining implementation options for the runtime customizable circuit. The design flow can also include generating, using computer hardware, a description of the circuit design using the runtime customizable circuit to implement the portion of the circuit design and generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within the integrated circuit. The program code is usable by the embedded processor to parameterize the runtime customizable circuit to create a specific instance of the runtime customizable circuit.

System design flow with runtime customizable circuits

A system includes a hardware offload circuit and a slave processor coupled to the hardware offload circuit. The system also includes a processor coupled to the slave processor and configured to execute productivity language instructions. The processor, in response to executing the productivity language instructions, is configured to generate commands and provide the commands to the slave processor. The slave processor, in executing the commands, is configured to monitor operation of the hardware offload circuit and control operation of the hardware offload circuit.

Productivity language interface for synthesized circuits

A system includes a runtime generator implemented in programmable circuitry of an integrated circuit, wherein the runtime generator is parameterizable at runtime of the integrated circuit to perform at least one of detecting a symbol pattern within a data stream or generating pseudo random number binary sequences. The system can include a processor configured to execute program code, wherein the processor is configured to provide first parameterization data to the runtime generator. In response to receiving the first parameterization data from the processor at runtime of the integrated circuit, the runtime generator implements a first automaton circuit configured to perform the at least one of the detecting the symbol pattern or the generating the pseudo random number binary sequences.

Runtime generators for regular expression matching and random number generation

An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay. The overlay circuit can include a trace buffer configured to receive a probed signal from circuitry within the overlay circuit. The trace buffer can be configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory. The integrated circuit also can include a processor coupled to the programmable circuitry and configured to control operation of the trace buffer. The processor can be configured to read the trace data from the runtime allocated memory.

Hardware trace and introspection for productivity platform using a system-on-chip

An integrated circuit can include a slave processor configured to execute instructions. The slave processor can be implemented in programmable circuitry of the integrated circuit. The integrated circuit also can include a processor coupled to the slave processor. The processor can be hardwired and configured to control operation of the slave processor.

Slave processor within a system-on-chip

A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

Runtime adaptive generator circuit

An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

Active interrupt handler performance monitoring in microprocessors

Techniques for efficient benchmarking. One method includes obtaining convergent results by performing a benchmarking test with a particular length to obtain a result (time), scaling the time exponentially, performing additional benchmarking tests, obtaining results for those tests, and determining whether the results scale linearly with length. Another method includes obtaining variance for non-convergent results by performing multiple sequences of benchmarking test. Within each new sequence performed, the benchmarking tests are spaced out further apart in time. If new maximum or minimum results are obtained, then further test sequences are performed and if no new maximum or minimum results are obtained after a threshold number of sequences, then the test ends. A device and computer-readable medium for performing benchmarking are also provided herein.

Intelligent and adaptive benchmark testing framework

A system includes a host data processing system and a target platform coupled to the host data processing system. The target platform includes an emulation system. The emulation system includes a processor system, an emulation circuit coupled to the processor system through an integrated circuit (IC) interconnect, and a performance monitor coupled to the IC interconnect. The emulation system receives, from the host data processing system, a software emulation model and a data traffic pattern. The emulation system emulates a system architecture by executing the software emulation model within the processor system and implementing the data traffic pattern over the IC interconnect using the emulation circuit. The emulation system provides, to the host data processing system, measurement data collected by the performance monitor during the emulation.

Performance analysis using configurable hardware emulation within an integrated circuit

Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.

Methods and circuits for debugging circuit designs

An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks implemented in the programmable logic. The method further includes obtaining a parameter set from the characterization database based on the description of the performance objectives. The method further includes generating a parameter image for setting registers of the processing system based on the parameter set.

Designing a system for a programmable system-on-chip using performance characterization techniques

Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing system to the IC. At least a portion of a boot process of the IC is automatically initiated, wherein the boot process uses the configuration data.

Growing community of inventors

Los Gatos, CA, United States of America

Patrick Lysaght