Hewlett-packard Development Company, L.P.

Compaq Computer Corporation, Inc.

Hewlett-packard Company

Patrick Lee Ferguson

Robert A Lester

John Edward Larson

John MacLaren

Robert C Brooks

Gary J Piccirillo

Jerome J Johnson

David J Maguire

Siamak Tavallaei

Jeffrey C Stevens

Christian H Post

Jeffrey S Autor

Charles N Shaver

Jeffery L Galloway

Paul B Rawlins

Tim W Majni

Benjamin H Clark

Dan Fink

Bret D Roscoe

Sompong Paul Olarig

David F Heinrich

Kenneth A Jansen

John S Thayer

Paul A Santeler

Robert S Wright

Robert L Woods

John D Battles

Robert A Scheffler

A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Power consumption limit associated with power over ethernet (POE) computing system

Power consumption limit associated with power over ethernet (PoE) computing system

Electronic circuits and methods are provided for conserving power within computers and other apparatus. A logic circuit performs a logical operation on a plurality of variables thus deriving a corresponding output. The output is used to drive and maintain an open or closed state of an electronic switch, accordingly. The electronic switch is disposed between a source of electrical energy and a system power buss of a computer. The computer can assume very low power, full power and other respective operating modes in accordance with the present state of the electronic switch.

Power switch control circuitry isolating or coupling a system power bus of a computer based on a result state of a logical operation

A first resistance () within a power supply () can be connected to a power supply output (). A variable resistance () can be serially coupled with the first resistance, thereby providing a first intermediate voltage at a point () disposed between the first resistance and the variable resistance. The variable resistance can be at a maximum in the absence of an expansion device () and at less than maximum in the presence of an expansion device. The first intermediate voltage and a second intermediate voltage () can be introduced to a comparator (). The comparator can provide an output signal () when the first intermediate voltage exceeds the second intermediate voltage. The comparator output signal can be used to confirm the power supply capacity to power an external device () and to enable one or more external device functions.

Variable adapter ID circuit

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Error indication in a raid memory system

A communication system for extending range of USB communications that may include a host computer system having a USB host controller, a USB hub, and transmitter circuitry. The USB host controller may be configured to operate using a split transaction for the USB communications. The communication system may also include receiver circuitry that receives a non-USB format of USB communication signals as the signals appear between split start and split complete transaction operations at the host computer system. The transmitter circuitry may be configured to forward the non-USB formatted USB communication signals across an extension between the transmitter circuitry and the receiver circuitry. At least one USB user interface device may be communicatively coupled to the receiver circuitry and receives USB communication signals from a receiver hub in the receiver circuitry. The USB communication signals correspond to the non-USB formatted communication signals that appear between the split start and split complete transaction operations at the host computer system.

USB interface extension through split transaction protocol

A method of sharing user resources in a computer system through a universal serial bus (USB) interface. The method may involve, not necessarily in this order, associating at least one USB device with a first user and at least another USB device with a second user; assigning the first user to a first USB port; assigning the second user to a second USB port; permitting the first user to temporarily assume control of the computer system through the first USB port for operation of the at least one USB device; and blocking the second user from access to the computer system while the first user has temporary control of the computer system.

User resource sharing through the USB interface

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion across on a plurality of memory cartridges each containing a plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). Each memory cartridge includes an independent memory controller and a corresponding control mechanism in the host/data controller to interpret the independent transitioning of each memory cartridge between various states, including a redundant-ready and a powerdown state to facilitate 'hot-plug' capabilities utilizing the removable memory cartridges. Fault information may be passed between the individual memory controllers and the host/data controller to facilitate expedient fault isolation.

Redundant memory sequence and fault isolation

A KVM extension configuration that includes a host connected to a transmitter for transmitting communication signals across an extension to a receiver where user interface devices are located. The host has a motherboard that supports USB communications. A USB adapter may be coupled to the transmitter that converts USB signals that the transmitter receives from the host to a non-USB format prior to transmission across the extension to the receiver where the user interface devices successfully communicate with the host. A transmitter core may be coupled to the transmitter that receives the non-USB signals from the USB adapter and transmits such signals to the receiver.

KVM extension configuration including a USB-to-non-USB adapter to support transmission of USB signals from a host to KVM devices located outside of USB operating ranges

A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue. If a memory location is rewritten with new data prior to scheduled scrub corresponding to the same address location, the controller will cancel the scrub to that particular memory location.

Real-time hardware memory scrubbing

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate &ldquo;hot-plug&rdquo; capabilities utilizing its removable memory cartridges.

Raid memory

A KVM extension configuration that includes a host connected to a transmitter for transmitting communication signals across a KVM extension to a receiver where user interface devices are located. The host has a motherboard that supports USB communications. The KVM extension configuration includes a USB host controller at the receiver that initiates data reads and writes to the host as delayed transactions and supports USB protocol communication with a plurality of the user interface devices. The configuration also includes a transmitter core in the transmitter having shadow registers that include content that is copied from the configuration registers of the USB host controller at the receiver. The host successfully carries out USB communications with the transmitter through the use of the content of the shadow registers. In addition, the receiver periodically synchronizes the content of the shadow registers with content from the configuration registers of the USB host controller.

Extension of USB functionality through shadowing of a remote USB host controller

A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

Memory data verify operation

A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the

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Cypress, TX, United States of America

Patrick Lee Ferguson