Bull S.a.

Buh Hn Information Systems Inc.

Bull Sas

Patrick Le Quere

The invention relates to a method for speeding up the time required to perform a Montgomery product calculation by applying the High-Radix Montgomery method on computing hardware. A loop of operations is performed consisting in repeating successive operations, i.e.: a first addition operation involving the addition of a value of one of several first products, designated ai&#xb7;b and a value of one variable, designated u, according to a first relationship u:=u+ai&#xb7;b; and a second addition operation involving the addition of a value of one of several second products, designated m&#xb7;n, and a value of variable u according to a second relationship u:=u+m&#xb7;n. At least the first and second addition operations are Carry-Save addition operations in order to speed up the time required to perform an addition.

Method and device for reducing the time required to perform a product, multiplication and modular exponentiation calculation using the Montgomery method

A module for secure management of digital data by encryption/decryption and/or signature/verification of signature which can be used for dedicated servers. The module is controlled by a microprocessor (&#x3bc;P). A working memory (RAM) is associated with the microprocessor and is provided with a common interfacing module. Parallel-connected to this common interfacing module and forming the internal circuits of said module are a plurality of circuits for secure management of data received from or respectively transmitted to the common interfacing module. Each secure management circuit forming an automatic secure management device is equipped with a secure management input/output sub-module connected to the common interfacing module and a specific sub-module for encryption/decryption or respectively for calculation/verification of signature.

Module for secure management of digital date by encryption/decryption and/or signature/verification of signature which can be used for dedicated servers

An encryption circuit for simultaneously processing various encryption algorithms, the circuit being capable of being coupled with a host system hosted by a computing machine. The circuit comprises an input/output module responsible for the data exchanges between the host system and the circuit via a dedicated bus. An encryption module coupled with the input/output module is in charge of the encryption and decryption operations. Isolation means between the input/output module and the encryption module makes the sensitive information stored in the encryption module inaccessible to the host system and ensures the parallelism of the operations performed by the input/output module and the encryption module. The circuit is supported on a peripheral component interconnect card. The circuit is specifically adapted to provide 'hardware' protection of computer servers or stations.

Architecture of an encryption circuit implementing various types of encryption algorithms simultaneously without a loss of performance

A high-speed random number generator ( ) comprising a physical random number generator, having a data input, an output and a pseudo-random generator coupled to the output of the physical random generator. The pseudo-random generator has an input adapted to receive a germ delivered by the physical generator and deliver at an output a pseudo-random output signal. The physical generator comprises a logic circuit that includes at least a data input (D) and a clock input (CLK), the data input (D) receiving a first &ldquo;high frequency&rdquo; clock signal H and the clock input (CLK) receiving a second &ldquo;low frequency&rdquo; clock signal H , with the &ldquo;high frequency&rdquo; signal H being sampled by the &ldquo;low frequency&rdquo; signal H . The two clock signals H and H are of different frequencies respectively and issue from two different first (OSC and OSC ) operating asynchronously from one another and not adhering to the setup time of the logic circuit ( ). The logic circuit is arranged to deliver at an output a signal in an intermediate state qualified as metastable between &ldquo;0&rdquo; and &ldquo;1&rdquo; and being constituted by a random number sequence. The metastability of the signal obtained as an output from the logic circuit ( ) is accentuated by phase noise of the first oscillator (OSC ) generating the &ldquo;high frequency&rdquo; signal H . The pseudo-random generator is arranged to re-inject part of the pseudo-random output signal into the physical generator. An internal memory stores the random numbers obtained as output signals from the pseudo-random generator. The two generators run on the same second &ldquo;high frequency&rdquo; clock H generated by the external oscillator ( ).

High speed random number generation

A controller (CTMI) for multiple transfer of data organized by a microprocessor (MPU) between a plurality of memories (SRAM, VRAM) and a computer bus (PSB), including a plurality of registers (REGI, REGO) programmed by the microprocessor for writing into them of information enabling the organization of the transfer over a first and a second channel. The controller includes a central bus (BC, BC1) connected to each of the registers; a first and a second channel controller, associated with the first and second channel, respectively; and an arbitration device connected on the one hand to the second interface and on the other to each of the channel controllers. The arbitration device allocates a given channel to the data routes going to the memories or the microprocessor. The channel controllers control, for each channel, the writing access of the microprocessor to the registers associated with that channel and the transfer of data to each of the memories.

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Villebon sur Yvette, France

Patrick Le Quere