Ascend Communications, Inc.

Patrick L DeAngelis

Mahesh N Ganmukhi

Brian Branscomb

Thomas Andrew Hoch

John Patrick Jones

Andrew T Hebb

Raymond Schmidt

Ronald Louis Baracka, Jr

Siu Wing Li

Eric L Reed

Raymond J Schmidt, Jr

A method is presented which allows for the testing and verification of an off-line switch fabric used in network switch having redundant switch fabrics. A special test cell is directed to the off-line switch fabric, loops through a portion of the switching core of the off-line switch fabric, and is returned from the off-line switch fabric. A plurality of test cells can be used to provide full mesh connectivity checking of the off-line switch fabric. Testing is accomplished without need for reconfiguration of the off-line switch fabric, and the off-line switch fabric is available for use immediately upon determination of the need therefor.

Switch fabric testing

An apparatus and method for enabling the combination of multiple streams of data cells into a single thread. By enabling plural input ports of an intermediate device to access a single parallel output port of the device, plural network switch elements share a single thread through a switch fabric. For instance, the method and apparatus permit interleaving the relatively low bandwidth cell outputs of two ATM network switch central control processors onto a single thread routed through an interconnected switch fabric. Certain of these cells are received from the switch fabric at a parallel input of the intermediate device, then routed to one of plural serial output ports. Pacing of cells provided to the plural serial input ports prevents exceeding the shared thread bandwidth.

Cell combination to utilize available switch bandwidth

The present invention is directed to an apparatus and method for efficiently transferring asynchronous transfer mode (ATM) cells across a backplane in a network switch. The present invention is realized through an electrical apparatus that converts parallel data that is received on parallel data input ports to serial data that is transmitted on serial data output ports. The parallel data that is received on each parallel data input port is divided and transmitted from a corresponding pair of serial data output ports. The electrical apparatus also converts serial data that is received on serial data input ports to parallel data that is transmitted on parallel data output ports. The serial data that is received on a corresponding pair of serial data input ports is combined and transmitted from a parallel data output port.

Apparatus and method for efficiently transferring ATM cells across a backplane in a network switch

A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM provides a primary external synchronization clock; a standby TM provides a redundant timing function. Both TMs access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock and phase-locked loop (PLL) on each TM. The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs.

Timing synchronization and switchover in a network switch

A module interconnection system which minimizes electronic signal propagation delays is disclosed. The module interconnection system includes a backplane, a first plurality of connectors arranged in a side by side generally parallel arrangement, and a second plurality of connectors arranged in a side by side generally parallel arrangement. In a preferred embodiment, the second plurality of connectors are mounted on the backplane at right angles to the first plurality of connectors so as provide short routing paths between each of the second plurality of connectors and at least one of the first plurality of connectors. Point-to-point signal interconnections are selectively utilized to provide data paths between selected contacts of at least one of the first plurality of connectors and selected contacts of the second plurality of connectors. The above described interconnection apparatus permits high speed data communication between modules disposed in at least one of said first plurality of connectors and at least one module disposed in said second plurality of connectors.

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Northborough, MA, United States of America

Patrick L DeAngelis