Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Patrick Knebel

Kevin Safford

Russell C Brockmann

Stephen R Undy

Blaine Douglas Gaither

Karl P Brummel

Joel D Lamb

Gregg Bernard Lesartre

Donald Charles Soltis, Jr

Rohit Bhatia

John William Bockhaus

Gregory L Ranson

Jeremy Petsinger

Paul L Perez

Bruce A Long

Dale Calvin Morris

Russ William Herrell

William Louie Walker

Douglas Benson Hunt

Jonathan P Lotz

Erin Antony Handgen

Steven T Mangelsdorf

Eric R DeLano

Matthew B Lovell

Christophe De Dinechin

Judson Eugene Veazey

Mark M Gibson

Thomas R Hotchkiss

Craig A Gleason

Robert E Naas

Mark A Forsyth

Pavel Vasek

Darius F Tanksalvala

R Craig Simpson

Mark R Storey

M A Susith Rohana Fernando

A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

Cache and method for cache bypass functionality

An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.

Computer workload migration using processor pooling

A system comprises a processor core and a cache coupled to the core and comprising at least one cache way dedicated to the core, where the cache way comprises multiple cache lines. The system also comprises a cache controller coupled to the cache. Upon receiving a data request from the core, the cache controller determines whether the cache has a predetermined amount of invalid cache lines. If the cache does not have the predetermined amount of invalid cache lines, the cache controller is adapted to allocate space in the cache for new data, where the space is allocable in the at least one cache way dedicated to the core.

Allocating space in dedicated cache ways

Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.

Servicing memory read requests

Coherency directory updating is provided in a multiprocessor computing system. A plurality of memory resources have a directory, and are operably connected to an interconnect fabric. A cell is operably connected to the interconnect fabric. The cell has a cache including an entry for each of a plurality of coherency units, each coherency unit included in a memory block representing a contiguous portion of the plurality of memory resources. A controller is operably connected to the interconnect fabric. The controller is configured to control a portion of the plurality of memory resources, and has a comparator configured to identify whether a memory block is local. If the memory block is local, the controller is configured to set a state of the directory to exclusive for a write transaction. If the memory block is not local, the controller is configured to set the state to invalid for a write transaction.

Coherency directory updating in a multiprocessor computing system

A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the second device.

Performing a memory write of a data unit without changing ownership of the data unit

The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Method and apparatus for implementing two architectures in a chip

An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparing the native state and the emulated state. Corresponding to the apparatus, a method verifies the correctness of a processor behavioral model, where the processor operates in a native mode state and an emulated mode state. The method includes determining if a macroinstruction to be executed is a native instruction, and, if the macroinstruction is a native instruction, executing the native instruction, the execution producing the native mode state of the processor. The method further includes, if the macroinstruction is not a native instruction, fetching the macroinstruction, providing microinstructions corresponding to the macroinstruction, and executing the microinstructions, the execution producing the native mode state of the processor. Finally, the method includes executing the macroinstruction, the execution producing an emulated state of the processor, and comparing the native mode state the of the processor with the emulated state of the processor.

Method and apparatus for verifying the correctness of a processor behavioral model

The present invention is a method for processing instructions by decomposing a macroinstruction into at least two microinstructions, executing the microinstructions in parallel, and linking the microinstructions such that they appear as though they were executed as a single functional unit. The present invention operates by determining whether certain exceptions occur in either of the functional units, according to SSE rules for exceptions. If an exception does occur in any of the linked microinstructions, then the execution of each of those microinstructions is canceled. This avoids the necessity of a back-off or undo mechanism.

Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions

An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.

Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions

A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address. A method and apparatus according to the present invention further allows flushing of the pipeline when conditions other than ones involved in branch instructions occurs, e.g., to flush stale instructions.

Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition

Methods for emulating an instruction set extension, comprising providing data to be operated upon, executing a first instruction with respect to a first portion of the data without committing the results of the first executed instruction, if no unmasked exceptions occur with respect to the first portion of the data, executing a second instruction with respect to a second portion of the data, and if no unmasked exceptions occur with respect to the second portion of the data, committing the results of the second executed instruction and again executing the first instruction with respect to the first portion of the data. If the first instruction is executed again, its results are committed. A handler is invoked if an unmasked exception occurs.

Method and apparatus for emulating an instruction set extension in a digital computer system

A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack registers may be executed in parallel. The system operates such that it can be determined whether a stack underflow exception has occurred and if it has, the move instructions can be flushed, and a micro-code handler algorithm invoked that operates to allow execution of the move instructions in parallel without a stack underflow exception.

Methods and apparatus for exchanging the contents of registers

An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage, replacing the normal sequence of microinstructions for a given macroinstruction. In order to execute the microinstructions, the test writer can issue the macroinstruction. The method may be implemented in a simulation model where one set of microinstructions in the reprogrammable microcode storage can be easily replaced. The method may also be applied to an actual microprocessor implementation.

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Ft. Collins, CO, United States of America

Patrick Knebel