Mayo Foundation for Medical Education and Research

Patrick Joseph Zabinski

Barry K Gilbert

Clifton R Haider

Rick Allen Philpott

Gary Scott Delp

Gregory A Worrell

Michael John Degerstrom

Daniel J Schwab

Christopher L Felton

Mark E Vickberg

This specification discloses a brain electrode device. The brain electrode device includes a set of contact points and a set of sub-circuits. The sub-circuits include sensor ports configured to connect to the contact to the respective ones of the contact points. The device can further include an intelligent multiplexer that aggregates signals from the set of sub-circuits and generates an aggregate signal. The aggregate signal is transmitted to a signal acquisition device.

Scalable multi-resolution electrode array for sensing and stimulating the brain

A fall detection system includes a plurality of sensors in which at least one of the sensors is coupled to or disposed near a floor. The fall detection system further includes a central monitoring system in signal communication with the plurality of sensors. The central monitoring system is configured to receive a response signal in response to an activation signal being transmitted from at least one of the plurality of sensors, and determine whether the response signal is indicative of a person being arranged in a prone position on the floor.

Proximity based fall and distress detection systems and methods

A system and method is presented for reducing skew between the positive and negative components of a differential signal in a high speed communications link. The communications link includes a signal generator producing and transmitting complementary positive and negative signals over separate transmission lines and a receiver receiving the complementary signals. The communication link further includes a skew compensation circuit having a skew detector, a controller, and separate delay and buffer elements for both the positive and negative component of the differential signal. The controller separately controls each of the delay or buffer elements in response to the detected skew between differential signal components.

Differential communication link with skew compensation circuit

A termination block for connecting a first signal device and a second signal device. The termination block includes a housing, first and second pair of connectors, and an electrical circuit having passive elements that connect the first and second pair of connectors and provide impedance matching.

Differential signal termination block

A termination block provides a pair of coaxial connectors for a differential signal source and a pair of coaxial connectors for connection to a single ended coaxial input. Passive electrical components provide impedance matching while maintaining phase-matched true and complement signal paths for the differential signal.

A circuit for aligning the phase of a parallel data signal to a clock signal. The circuit includes a parallel data terminal for receiving a parallel data signal formed by multiple word bits, a clock terminal for receiving a clock signal, and a data ready terminal for receiving a data ready signal which has a logic state transition aligned with a first information bit of the parallel data signal. A plurality of data signal delay and sampling circuits connected to the clock terminal and the parallel data terminal provide time-slice bit samples of each information bit of the parallel data signal. A comparator and decision circuit coupled to the clock terminal and at least one of the data signal delay and sampling circuits compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal. A multiplexer circuit coupled to each data signal delay and sampling circuit and to the comparator and decision circuit outputs the selected time-slice bit sample of each word bit of the parallel data signal as the phase-aligned parallel data signal. A first-bit intialization circuit connected to the clock terminal and the data ready terminal and coupled to the multiplexer causes the time-slice bit samples corresponding in time to the logic state transition of the data ready signal to be outputted as a first one or more information bits of the phase-aligned data signal before the comparator and decision circuit operates to compare and select one of the plurality of time-slice bit samples.

Growing community of inventors

Stewartville, MN, United States of America

Patrick Joseph Zabinski