Seagate Technology Incorporated

Other

Patrick Joseph Ryan

Song Sheng Xue

Kaizhong Gao

Nurul Amin

Shaoping Li

Paul E Anderson

James F Dolejsi

Konstantin Nikolaev

Steven Kalderon

Dimitar Velikov Dimitrov

Haiwen Xi

Xuefei Tang

Michael C Kautzky

Mark Thomas Kief

Peter Crane

Lei Zhang

Michael Xuefei Tang

Yuming Zhou

Zheng Gao

Wayne Allen Bonin

Hans L Leuthold

Ming Sun

Sining Mao

Dadi Setiadi

Brian Lee

John Robert Pendray

Qing I He

Richard August Budde

Andrew D White

Bradley Jay Ver Meer

Kevin Richard Heim

Johannes Van Ek

Roger L Hipwell

Jeffery K Berkowitz

Cal E Hardie

Kevin Jon Schultz

Daniel E Glumac

Clifton H Chang

Peter Thomas Weyandt

Bryan K Oliver

Yuankai Zheng

Yiran Chen

Antoine Khoueir

Olle Gunnar Heinonen

Ladislav Rudolf Pust

Ned Tabat

Allan E Schultz

Richard P Larson

Peter K George

Feng Y Wang

Anthony M Mack

Christopher James Rea

James Keith Price

William P Wood

Andrzej Adam Stankiewicz

Pu-Ling Lu

Alan Biggar Johnston

Sunita B Gangopadhyay

Taras Grigoryevich Pokhil

Greg S Mowry

William Paul Vavra

Steven Paul Bozeman

William J O'Kane

Rod V Bowman

Janusz Jozef Nowak

Juren Ding

Yiming Shi

Michael R Montemorra

Bogdan M Simion

Alan B Johnston

Duane C Phinney

Zhijun Yang

Nural Amin

Songsheng Xue

Juan Fernandez-deCastro

Paul Edward Anserson

Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

Non-sequential encoding scheme for multi-level cell (MLC) memory cells

An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction.

Non-volatile memory cell with lateral pinning

A magnetoresistive device includes a free layer, a separating layer, a pinned layer, and a magnetic stabilizer in close proximity to the pinned layer, wherein the magnetic stabilizer may enhance the stability of the magnetization direction of the pinned layer.

Magnetoresistive device with enhanced pinned layer

A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.

Magnetic memory with porous non-conductive current confinement layer

A magnetic sensor includes a reference layer having a first magnetization direction and a free layer assembly having an effective magnetization direction substantially perpendicular to the first magnetization direction and substantially perpendicular to a plane of each layer of the free layer assembly. A spacer layer is between the reference layer and the free layer, and a signal enhancement layer is exchange coupled to the free layer assembly on a side opposite the spacer layer.

Magnetic sensor including a free layer having perpendicular to the plane anisotropy

Method and apparatus for tuning a variable resistance resistive sense element of an electronic device. In some embodiments, a value indicative of a selected number of consecutive pulses is stored in a memory location and a resistive sense element (RSE) is set to a baseline RSE resistance. A tuning operation is performed by applying the selected number of consecutive pulses to the RSE to tune the baseline RSE resistance to a final adjusted resistance.

Tuning a variable resistance of a resistive sense element

Various embodiments of the present invention are generally directed to an apparatus and method associated with a semiconductor device with thermally coupled phase change layers. The semiconductor device comprises a first phase change layer selectively configurable in a relatively low resistance crystalline phase and a relatively high resistance amorphous phase, and a second phase change layer thermally coupled to the first phase change layer. The second phase change layer is characterized as a metal-insulator transition material. A programming pulse is applied to the semiconductor device from a first electrode layer to a second electrode layer to provide the first phase change layer with a selected resistance.

Semiconductor device with thermally coupled phase change layers

A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer positioned between the specular layer and the sidewall.

Magnetoresistive device having specular sidewall layers

Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.

High bandwidth package

A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer is positioned between the specular layer and the sidewall.

A micro-electromechanical systems (MEMS) disc drive includes high-precision and integrated components to allow for increased functionality, robustness and reduced size as compared to currently produced disc drives. Integrating multiple subcomponents of the disc drive using batch processing provides low manufacturing costs. Furthermore, using MEMS techniques, new features can be added to disc drives. For example, an environmental control component, an accelerometer and/or a thermometer may be integrated into the housing of the disc drive.

MEMS disc drive

A magnetoresistive stack includes a free layer, a separating layer, a pinned layer, and a magnetic stabilizer in close proximity to the pinned layer such that such that the magnetic stabilizer enhances the stability of the magnetization direction of the pinned layer.

Magnetoresistive stack with enhanced pinned layer

In general, the invention is directed to techniques for integrated interconnects with a set of disc drives. The interconnects allow for a set of disc drives to be positioned in an array; for example, as set of disc drives may be stacked to communicate with a device through a single interface of the device. The interconnects may be formed as vias within the housing of the disc drives. Vias may produced using MEMS techniques, e.g., electroplating, as part of the manufacturing processes of the disc drive itself.

Interconnect architecture for disc drive array

Growing community of inventors

Saint Paul, MN, United States of America

Patrick Joseph Ryan