Intel Corporation

Patrick John Ott

Rachael Jade Parker

Gregory F Taylor

Martin Spence Denham

Mark L Neidengard

Kaizad Rumy Mistry

Wenliang Chen

Mohsen Alavi

Paul Gregory Slankard

Embodiments of the present invention include a circuit, a method, and a system for power-on detect circuitry for use with multiple voltage domains.

Power-on detect circuit for use with multiple voltage domains

A high voltage tolerant ('HVT') power up detector. The HVT power up detector includes a voltage detector circuit coupled to a high voltage tolerant transistor ('HVTT'). The voltage detector circuit determines when a voltage supply is above a threshold logic level voltage. The HVTT has a gate coupled to receive a logic level voltage and a source and a drain to couple between the voltage supply and the voltage detector circuit. The HVTT shelters the voltage detector circuit from voltages above the logic level voltage when the voltage supply exceeds the logic level voltage.

High voltage tolerant power up detector

A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.

Static, low-voltage fuse-based cell with high-voltage programming

A fuse cell comprises a plurality of fuse elements, a plurality of cascode configuration programming circuits correspondingly coupled to the fuse elements, and a plurality of cascode configuration sensing circuits correspondingly coupled to the fuse elements.

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Hillsboro, OR, United States of America

Patrick John Ott