Cadence Design Systems, Inc.

Silicon Perspective Corporation

Patrick John Eichenseer

Thaddeus Clay McCracken

Ping-Chih Wu

Hsi-Chuan Chen

Kit Lam Cheong

Ricky Lewelling

Cecile Nghiem

Ziad Sadi

Jong-Chang Lee

Wei-Jin Dai

Dennis Huang

Kit-Lam Cheong

Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Method and system for conducting design explorations of an integrated circuit

Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.

Method and system for designing a timing closure of an integrated circuit

In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a 'master module' and the others designated 'clone modules'. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N&#x3e;0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.

Trial placement system with cloning

When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout. The partitions are then separately placed and routed a manner consistent with the spatial and timing constraints imposed on each partition by the floor plan and the timing budget.

Method for generating a partitioned IC layout

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Austin, TX, United States of America

Patrick John Eichenseer