Freescale Semiconductor,inc.

Motorola Corporation

Patrick James McGuinness

Alexander Mikhailovich Marchenko

Robert L Maziasz

Mikhail Anatolievich Sotnikov

Vladimir Pavlovich Rozenfeld

Andrey P Plis

Andrei Vladimirovitch Zinchenko

Michael Viacheslavovich Golikov

A method for incorporating aging effects into the static timing analysis of a design of an integrated circuit includes determining aging factors for the arc-state pairs of standard cells. The aging factors may include nominal aging factors and variational aging factors reflecting on chip variation aging effects. State profiles are determined for each cell instance in the design. The state profile for a cell instance indicates probabilities for each possible state that the cell may occupy. Based on the instance-specific state profiles and the aging factors, instance-specific aging factors are derived. The instance-specific aging factors may then be converted into instance-specific aging effect timing values. The instance-specific aging effect timing values may then be used to generate instance-specific static timing models, which may be used to perform static timing analysis.

Static timing analysis adjustments for aging effects

A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.

Method for automated transistor folding

A channel routing method ( ) comprises computing channel parameters ( ), classifying a channel complexity and estimating a channel height ( ), optionally, determining a trunk placement direction ( ), assigning tracks and layers ( ), determining a quality function QF ( ), and optimizing ( ). The channel complexity is classified using predetermined weighting parameters (a to a ). This classification selects a significance vector n. In the assigning step ( ), the vector n is combined with the channel parameters to a criterion. The criterion is used the select the most suitable assignment. In repetitions of assigning, determining QF and optimizing steps, the significance vector n and, optionally, QF are modified. The repetition are stopped upon compliance of a breaking condition which can refer to QF.

Method for channel routing, and apparatus

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Austin, TX, United States of America

Patrick James McGuinness