Lsi Logic Corporation

Adeia Semiconductor Bonding Technologies Inc.

Lsi Corporation

Patrick J Variot

Chok J Chia

Qwai Hoong Low

Maniam B Alagaratnam

Robert T Trabucco

Hong Shen

Seng-Sooi Allen Lim

Manickam Thavarajah

Adrian S Murphy

Seng Sooi Lim

Teresa Dalao

A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference ('EMI') shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.

3D-interconnect with electromagnetic interference ('EMI') shield and/or antenna

A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

Region shielding within a package of a microelectronic device

A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.

3D-interconnect

A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.

A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package. The conductive structure may be patterned to form external contacts. At least some of the external contacts may overlie the microelectronic element.

A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Electronic device package and method of manufacture

A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g., using wire bonds between the trace and a nearby selected via, thereby allowing each pad of the IC die to be selectively connected to a desired via, and hence to a selected solder ball or pin.

Method for programming a substrate for array-type packages

A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.

Molded tape ball grid array package

A semiconductor package (,) includes a bondable aluminum heatspreader (,) made from anodized aluminum, thereby forming an anodization layer (,) on the surface of the heatspreader. Portions of the anodization layer are removed, e.g., by grinding, in order to provide an attachment area (,) to which a wire (,) or beam may be bonded in order to electrically connect the heatspreader to a desired voltage potential, such as a ground potential or a positive or negative potential. The heatspreader is thermally bonded to a semiconductor die (,) housed within the package. The anodized aluminum heatspreader thus not only removes and dissipates heat from the semiconductor die, but also functions as a voltage or ground plane within the semiconductor package.

Bondable anodized aluminum heatspreader for semiconductor packages

An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.

Electrostatic protected substrate

An apparatus and method are presented for testing an adhesive layer formed between an integrated circuit and a plate, wherein the plate may be semiconductor device package substrate or a heat spreader. The apparatus includes a pull stud and a pull arm. The pull stud has an upper portion and a lower portion, wherein the lower portion is attached to a surface of the integrated circuit opposite the plate. The upper portion of the pull stud may be, for example, a tapered cylinder having a large end and a small end. The small end meets the lower portion of the pull stud. The pull arm has two opposed ends and at least one bracket for receiving a force. One of the pull arm ends has a 'V'-shaped opening surrounded by a lip which receives the upper portion of the pull stud. During use, the lip contacts and retains the upper portion of the pull stud. The opening has an upper wall, and an upper surface of the pull stud contacts the upper wall when the upper portion of the pull stud is inserted into the opening. The lip is vertically displaced from the upper wall such that the lip contacts the upper portion of the pull stud a spaced distance from where the upper surface of the pull stud contacts the upper wall of the opening. In this way, the pull stud and the pull arm are substantially mechanically locked together during use of the apparatus.

Apparatus and method for testing a flip chip integrated circuit package

A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.

Electroplating fixture for high density substrates

A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount. Additionally, the planarized solder ball contacts locally compensate individually for warpage of the integrated circuit package by variation in the individual dimensions of dependency of each solder ball below the bottom surface of the package.

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San Jose, CA, United States of America

Patrick J Variot