Micron Technology Incorporated

Micron Semiconductor, Inc.

Patrick J Mullarkey

Casey R Kurth

Michael Amiel Shore

Scott James Derner

Daryl L Habersetzer

Jason E Graalum

Kurt D Beigel

Douglas John Cutter

Fan Ho

Kim M Pierce

Brett M Debenham

Dien S Luong

Adrian E Ong

Timoty B Cowles

Jeffrey P Wright

Seth A Eichmeyer

Mohamed A Imam

Todd A Merritt

Huy Thanh Vo

Hua Zheng

Aron T Lunde

Tim Cowles

Timothy B Cowles

Computer-readable media and methods for a geospatial image map are disclosed. A computer-readable medium has computer-readable instructions stored thereon. The computer-readable instructions are configured to instruct one or more processors to display a map of a selected geographic region on an electronic display. The map includes geographic sub-regions displayed within the map. The computer-readable instructions are configured to instruct the one or more processors to select discrete images corresponding to the geographic sub-regions, and display the discrete images at the same time on the electronic display as an overlay to the map. A method includes displaying a map of a selected geographic region, displaying geographic sub-regions of the selected geographic region, selecting discrete images corresponding to the geographic sub-regions and one or more selected categories, and displaying the discrete images simultaneously on the electronic display as an overlay to the map.

Computer-readable media and methods for generating a geospatial image map

Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.

Apparatus and techniques for programming anti-fuses to repair a memory device

A system, apparatuses such as a non-transitory readable medium, and a method for generating a geospatial interactive composite web-based image map are disclosed. The system may be configured to receive, from a user device, a request for creating a geospatial interactive composite web-based image map for a selected region of map data displayed by the user device, select images responsive to the request corresponding to defined sub-regions within the selected region of the map data displayed by the user device, construct a collage for the geospatial composite web-based image map responsive to selecting the images, and transmit the collage to the user device for display thereon as an overlay to the map data.

System, apparatus, and related method for generating a geospatial interactive composite web-based image map

Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

Systems and methods for memory cell array initialization

Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

Circuits, apparatuses, and methods are disclosed for address scrambling in integrated circuits. One example apparatus includes a plurality of data regions, each of the plurality of data regions configured to provide a respective portion of data responsive to a physical address provided by a respective decode circuit. The plurality of data regions are configured to provide their respective portions of data responsive to a common logical address. The common logical address is scrambled such that a plurality of different physical addresses are provided to the plurality of data regions.

Circuits, apparatuses, and methods for address scrambling

Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.

Methods and memory devices for repairing memory cells

Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Method and apparatus for checking the resistance of programmable elements

A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the half density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

Circuit for programming antifuse bits

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS

A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.

A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory. The method includes the steps of: connecting the antifuse in series with a node; providing current to the node through a parallel combination of a first transistor and a second transistor that is sufficient to charge the node from a first voltage to a second voltage; and detecting whether the voltage at the node charges to the second voltage or remains at the first voltage to indicate that the antifuse is programmed properly; outputting first and second signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is programmed properly.

Testing a memory device having M data pads with a tester having N<M data pads, comprising writing data to the memory device in a test configuration; then in a normal configuration reading the data and writing the data back to the memory device. Subsequently the memory device is configured to a test configuration and the data is read to the tester to check for error.

Growing community of inventors

Meridian, ID, United States of America

Patrick J Mullarkey