Lucent Technologies Inc.

Agere Systems Guardian Corp.

Patrick J Kelley

Ranbir Singh

Chung Wai Leung

Larry Bruce Fritzinger

Cynthia C Lee

John Simon Molloy

Richard Joseph McPartland

Ross Alan Kohler

A split gate memory cell is described which is fabricated from two-polysilicon layers and comprises a silicon substrate having a source and a drain electrode and a storage node, a tunnel oxide on the substrate, a first control gate electrode and a floating gate electrode spaced from each other and fabricated from the same polysilicon layer and a second control gate electrode of a second poly material formed between and over the first control gate and floating gate and isolated therefrom by a dielectric layer therebetween.

Split gate memory cell

A method of forming round corners for a gate oxide between a floating gate and a control gate of a memory cell comprises the steps of forming the floating gate over a tunnel oxide; forming a mask over the floating gate; forming rounded end caps adjacent distal ends of the mask; transferring the rounding of the end caps to top corners of the floating gate; forming the gate oxide over the floating gate; and, forming the control gate over the gate oxide. A memory cell having a rounded corner interface between the floating gate and control gate is also provided.

Method of manufacturing a flash memory cell having inter-poly-dielectric isolation

An electrically erasable memory device includes a substrate and a plurality of single poly layer memory cells in the substrate. Each single poly layer memory cell includes a first MOS transistor in a first region in the substrate and spaced apart source and drain regions. Each single poly layer memory cell further includes a capacitor having a first electrode overlying a second region in the substrate and an insulating layer therebetween, and a third region in the second region defining a second electrode. An erasing circuit selectively erases the single poly layer memory cell by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode of the capacitor. The first and second voltage references bias the first MOS transistor so that the third voltage reference for erasing the single poly layer memory cell does not cause a junction breakdown of the first MOS transistor.

Erasable memory device and an associated method for erasing a memory cell therein

A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).

Single-poly non-volatile memory cell having low-capacitance erase gate

A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench. During this process, the rounding of the end caps is transferred to the top corners of a trench.

Shallow trench isolation method providing rounded top trench corners

A method of fabricating a novel split gate memory cell comprises forming a tunnel oxide layer on a silicon substrate, forming a first conductive layer over said tunnel oxide layer, etching a trench in said conductive layer to divide said conductive layer into two separate layers with a space therebetween, one such layer to become a first gate electrode and the other separate layer to become a floating gate electrode of the device, forming a dielectric layer over the exposed surfaces, and depositing a second conductive layer which will become a second control gate electrode over said dielectric layer.

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Orlando, FL, United States of America

Patrick J Kelley