Analog Devices,inc.

Patrick J Garavan

Martin Gerard Cotter

Eanonn Byrne

A circuit is provided which is adapted to compensate for the inherent parasitic capacitance which is implicit in switched capacitor circuits. By shielding the parasitic capacitance to a common node of the circuit and then connecting this shield to a voltage source that tracks the voltage change at the input to an amplifier, the present invention provides a bootstrapping effect that enables a minimization of the effect of the parasitic capacitance. The invention also provides a circuit that is adapted to compensate for curvature in the output of a switched capacitor bandgap reference.

Switched capacitor bandgap reference circuit

A temperature sensor circuit is provided which is adapted to provide an indication of the temperature on a chip. The sensor includes a bandgap temperature sensor which is sequentially driven by a plurality of current sources. The current sources are shuffled so as to minimize problems associated with matching currents.

Method and circuit for the provision of accurately scaled currents

A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

Charge redistribution analog-to-digital converter with system calibration

Using a power-up delay circuit on an analog/digital converter integrated circuit (i.e., an analog-to-digital converter or a digital-to-analog converter) to generate a signal delayed from power-up, and initiating a calibration of the converter upon detecting the delayed signal. In preferred embodiments, calibration can also be initiated in response to a signal on a calibration input pin of the integrated circuit, and the duration of the delay can be derived from a reference (e.g., by charging an external capacitor with it) or from the duration of a calibration operation. Circuitry can be provided to automatically place the circuit in an operating mode upon power-up that keeps the integrated circuit in shutdown mode when it is not converting or calibrating.

Power-up calibration of charge redistribution analog-to-digital converter

Performing a coarse conversion of an analog signal to a coarse digital representation using a first analog-to-digital converter, transferring the coarse representation to a second converter, and performing a fine analog-to-digital conversion of the signal using the coarse representation as a starting value for a fine digital representation. The fine conversion can include a redundant portion that can be used to correct a mismatch between the coarse and fine conversions, and this correction can operate according to a combinatorial transfer function. The fine conversion may include switching from a coarse reference to a fine reference after transferring the coarse representation. The fine conversion can also include comparing an amount of charge in a sampling capacitor after performing the coarse conversion. Also disclosed is converting an analog signal to a digital representation having a first resolution level, adjusting a bandwidth of the converter circuit, and then continuing to convert the analog signal to a second, higher resolution level. The adjusting can include adjusting a bandwidth of a comparison circuit. Further disclosed is evaluating the amount of charge stored in a second sampling capacitor while tracking an analog signal with the first sampling capacitor. The amount of charge stored in the first capacitor is evaluated while tracking the signal with the second capacitor. Evaluating the amount of charge in the first capacitor can include comparing performed in part by a first comparator input stage, evaluating the amount of charge in the second capacitor can include comparing performed in part by a second comparator input stage. Analog-to-digital conversion circuitry can be multiplexed between the sampling capacitors.

Analog-to-digital conversion with multiple charge balance conversions

A method of operating a charge redistribution analog-to-digital converter. The method includes sampling a first voltage with a capacitive network, and then switching the plate of one of the capacitors in the network from a supply voltage node to a reference voltage node. After switching, a second voltage is sampled, and a quantity of charge stored in the capacitive network, which quantity results from both of the sampling steps, is tested. In another general aspect, a method of converting an analog voltage to a digital value, which includes sampling a charge related to the analog voltage, and precharging and charging capacitors in an array. The charge sampled in the step of sampling is then tested against a charge stored in the capacitors in the array.

Low-voltage CMOS analog-to-digital converter

A CMOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuity to reduce a quiescent voltage drop associated with the loading circuitry.

Low-voltage CMOS comparator with offset cancellation

A MOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuity to reduce a quiescent voltage drop associated with the loading circuitry.

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Limerick, Ireland

Patrick J Garavan