Xilinx, Inc.

Andapt, Inc.

Patrick J Crotty

John Birkner

Kapil Shankar

Herman Cheung

Tao Pi

Thomas Chan

Steven P Young

Hy V Nguyen

Jinsong Oliver Huang

Bernard J New

Austin H Lesea

James Karp

Ting Lu

Bradley L Taylor

Hassan K Bazargan

Maheen A Samad

William Edward Allaire

Scott S Nance

Fu-Hing Ho

Sandeep Dutta

Shashank Bhonge

Ranajit Ghoman

Arifur Rahman

Andy T Nguyen

Tim Tuan

Sridhar Subramanian

Alireza S Kaviani

Matthew H Klein

Hsung Jai Im

Henley Liu

Sridhar Narayanan

John G O'Dwyer

Richard C Li

James A Walstrum, Jr

Jae-Gyung Ahn

Minjong Kim

Sean W Kao

Paul G Hyland

Honggo Wijaya

Patrick T Lynch

Tony Le

Mark A Moran

A power management integrated circuit (PMIC) includes: a plurality of high voltage power field effect transistors (FETs); and a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs. The plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.

Power management integrated circuit integrating field effect transistors and programmable fabric

An integrated analog and digital adaptive platform includes: a plurality of adaptive analog blocks, each of the plurality of adaptive analog blocks being integrated with a respective digital wrapper; and a programmable digital fabric configured to programmably connect one or more of the plurality of adaptive analog blocks by connecting a plurality of digital wrappers integrated with the one or more of the plurality of adaptive analog blocks. The plurality of adaptive analog blocks that are programmably connected using the programmable digital fabric provide one or more programmable analog functions.

Adaptive analog blocks with digital wrappers integrated onto programmable fabric

A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.

Compensation memory (CM) for power application

A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.

Pulse-width modulation (PWM) control loop for power application

A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.

Programmable analog and digital input/output for power application

A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.

Programmable logic device with integrated high voltage power FET

An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

Method and apparatus for analog to digital error conversion with multiple symmetric transfer functions

A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

Precision modulation timer (PMT) integrated in a programmable logic device

A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

Noise-immune reference (NREF) integrated in a programmable logic device

A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power transistor and the programmable fabric, and a plurality of internal components. The plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper.

Scalable integrated MOSFET (SIM)

A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.

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San Jose, CA, United States of America

Patrick J Crotty