Qualcomm Incorporated

Patrick Isakanian

Darius Valaee

Satish Krishnamoorthy

Stephen Thilenius

Michael J Brunolli

Vaishnav Srinivas

Srivatsan Thiruvengadam

Yong Xu

Reza Jalilizeinali

Farrukh Aquil

Boris Andreev

Alvin Leng Sun Loke

Ashwin Sethuram

Kevin Jia-Nong Wang

Bo Yu

Prince Mathew

Vikas Mahendiyan

Ravindra Arvind Khedkar

Shashank Rajendra Prasad

Ercem Yesil

Stephen Clifford Thilenius

A system includes a driver including a pull-up p-type field effect transistor (PFET). The system also includes a negative boost circuit. The negative boost circuit includes a first drive circuit configured to receive a first supply voltage, a second drive circuit configured to receive a second supply voltage different from the first supply voltage, a switch coupled between an output of the second drive circuit and a gate of the pull-up PFET, and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the gate of the pull-up PFET and the second terminal is coupled to an output of the first drive circuit. The system also includes a pre-drive circuit configured to drive an input of the first drive circuit and an input of the second drive circuit based on an input signal.

Voltage boosted transmitter without a negative rail

A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.

Self-calibration of delay circuits in asynchronous loops

A method for equalizing a data signal includes providing a data signal to a pair of input transistors that provides an output signal, contributing to the output signal, a first current or voltage that has a magnitude determined by a first weighted feedback signal using a first decision-feedback circuit that includes a first pullup circuit coupled to a drain of a first input transistor, and a first pulldown circuit coupled to the drain of the first input transistor, and contributing to the output signal, a second current or voltage that has a magnitude determined by a second weighted feedback signal using a second decision-feedback circuit that includes a second pullup circuit coupled between a drain of a second input transistor and the first voltage rail, and a second pulldown circuit coupled between the drain of the second input transistor and a second voltage rail.

Parallel direct-feedback decision-feedback equalizer for high-speed low-voltage wireline links

An integrated circuit (IC) including a first transceiver interface circuit extending longitudinally in a first direction substantially perpendicular to a second direction parallel to edge of the IC, wherein the first transceiver interface circuit comprises a first T-coil; and a second transceiver interface circuit extending longitudinally in the first direction, wherein the second transceiver interface circuit is staggered from the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T-coil, and wherein the second T-coil is offset from the first T-coil along the first direction.

Integrated circuit integration of T-coils at interfaces to communication links

A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

Clock qualifier enhancement for external double data rate memory interfaces

An input stage of a comparator includes a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage, a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage, a third transistor coupled in series with the first transistor, and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage further includes a sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.

Clocked comparator with series decision feedback equalization

In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.

Decision feedback equalizer for low-voltage high-speed serial links

An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.

Timer-based edge-boosting equalizer for high-speed wireline transmitters

An aspect relates to an apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.

Circuit device aging assessment and compensation

An apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.

Certain aspects of the present disclosure provide methods and apparatus for equalizing a transmitter circuit for use in high-speed data links, such as in a serializer/deserializer (SerDes) scheme. One example transmitter circuit generally includes at least one driver stage, a first equalization circuit coupled to an output of the transmitter circuit, and a second equalization circuit coupled to an input of the at least one driver stage. One example method of transmitting data generally includes operating a transmit circuit comprising: at least one driver stage, a first equalization circuit coupled to an output of the transmitter circuit, and a second equalization circuit coupled to an input of the at least one driver stage; and selectively enabling at least one of the first equalization circuit or the second equalization circuit.

Equalization for a transmitter circuit

A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

Memory interface with adjustable voltage and termination and methods of use

A transmitter is provided with a plurality of pull-up legs and a plurality of pull-down legs. A controller controls the pull-up legs and the pull-down legs so that a constant output impedance is provided while supporting a range of logic-high output voltages.

Constant impedance transmitter with variable output voltage limits

An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

Growing community of inventors

El Dorado Hills, CA, United States of America

Patrick Isakanian