Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag

Infineon Technologies LLC

Infineon Technology Ag

Infienon Technologies Ag

Polaris Innovations Limited

Patrick Heyne

Thomas Hein

Torsten Partsch

Thilo Marx

Stefan Dietrich

Christian Weis

Dieter H&auml;rle

Michael Bernhard Sommer

Peter Schr&ouml;gmeier

Peter Schroegmeier

Sabine Kieser

Michael Markert

Thoralf Gr&auml;tz

Bret A Johnson

Rajashekhar Rao

Martin Brox

Helmut Schneider

Alessandro Minzoni

Thoai-Thai Le

Kazimierz Szczypinski

Aaron Nygren

Martin Buck

Ullrich Menczigar

Peter Schrögmeier

Musa Saglam

Thoralf Graetz

Dieter Haerle

Per Anders Johansson

Marx Thilo

Thomas Miller

Sabine Sch&ouml;niger Kieser

Thoralf Gra&euml;tz

Thoralf Gratz

Dieter Harle

A delay circuit includes a delay device, to which an input signal is supplied. A first phase-shifted signal can be generated by the delay device, which is delayed by a first delay time with respect to the input signal, and a second phase-shifted signal can be generated, which is delayed by a second delay time with respect to the input signal. The delay device is configured such that the first and second phase-shifted signal can be generated in inverted fashion with respect to one another at an output terminal of the delay device after a delay of the input signal by a delay time.

Delay circuit

A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.

Delay locked loop

A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.

Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal

The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

Read latency control circuit

A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.

Delay locked loop and method for setting a delay chain

The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

Method and circuit arrangement for resetting an integrated circuit

The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay apparatus with variably controllable delay period, in which a clock pulse or a signal derived from it, has a variably controllable delay period imposed on it and is then emitted as a delayed signal. In addition to the first delay apparatus with variably controllable delay period, a second delay apparatus with variably controllable delay period is provided.

Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process

A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.

Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device

A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.

An integrated synchronous memory has a register which can store a frequency-range information item regarding whether the memory is operated in a first or in a lower, second frequency range in an application. The mode of operation of a subcircuit in the memory can be controlled on the basis of the stored frequency-range information item in the register. A memory configuration having a memory module on which at least one such synchronous memory is disposed contains a controller which can be connected to the memory module and sets the register in the at least one memory. Therefore, optimum functionality of the memory can be ensured both in a high and in a low frequency range of the operating frequency.

Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory

An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock (CLKI), and outputs the data (D) with a specific phase shift (&#x394;TOUT) with respect to the first internal clock (CLKI), in synchronism with the external clock (CLKE), at a data connection (P). A counting unit (CT) starts a counting process for recording the number of successively following first levels of the first internal clock (CLKI) as soon as a second internal clock (CLKI), which is synchronized to the external clock (CLKE), for the first time assumes a first level while an output control signal (PAR) is at first level. It activates the output circuit (OUT) as soon as the number of successively following first levels of the first internal clock (CLKI) has reached a predetermined value.

Synchronous integrated memory

A method and logic/memory module set the desired corrected duty cycle between the time periods of the first and second level states of at least one control/reference signal. In that, the rising time period of the rising edge and/or the fall time period of the falling edge of the control/reference signal are increased and/or decreased (i.e. changed) by a predefinable correction time period.

Method and logic/memory module for correcting the duty cycle of at least one control/reference signal

A switching network with trimmable resistors lies in a control loop of a voltage generator that can be switched off from the supply voltage by a logic device. The logic device and also the switching network are driven by the same signals. The circuit configuration can be used for trimming or switching off the output voltage generated by the voltage generator during the functional test. As many settings as possible for the output voltage can be tested by a small number of control signals.

Circuit configuration for generating a controllable output voltage

The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.

Optimized-delay multiplexer

A delay device has multiplexers connected in series in a differential configuration. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal that is to be delayed can be supplied. A control signal controls the switch position of one of the multiplexers such that its output is connected to the input of the delay device. All the other multiplexers are in the other switch position. This results in the delay device producing a specific delay time. When used in a delay control loop, this results in a jitter-free output signal, even if the operating conditions are fluctuating.

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Munich, Germany

Patrick Heyne